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CY7C1347G
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2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW
Models:
CY7C1347G
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Electrical Characteristics
Block Diagram
Single Read Accesses
Weight
psoc.cypress.com/low-power
Features
Switching Characteristics
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Contents
Functional Description1
Features
CY7C1347G
Selection Guide
ADSC
Block Diagram
ADDRESS
REGISTER
CY7C1347G
Pinouts
CY7C1347G
Description
CY7C1347G
Table 1. Pin Definitions
Name
Functional Overview
Single Read Accesses
Single Write Accesses Initiated by ADSP
Single Write Accesses Initiated by ADSC
2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW
Table 5. Truth Table 2, 3, 4, 5
VDDQ
Electrical Characteristics
Maximum Ratings
Operating Range
AC Test Loads and Waveforms
Electrical Characteristics continued
Capacitance
Thermal Resistance
Switching Characteristics
Figure 5. Read Cycle Timing16
Switching Waveforms
Figure 6. Write Cycle Timing16
Switching Waveforms continued
Page 14 of
Figure 7. Read/Write Cycle Timing16, 18
19. GW is HIGH
ALL INPUTS except ZZ
21. DQs are in high-Z when exiting ZZ sleep mode
Ordering Information
Ordering Information continued
Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm
Package Diagrams
Figure 10. 119-Ball BGA 14 x 22 x 2.4 mm
Package Diagrams continued
Figure 11. 165-Ball FBGA 13 x 15 x 1.4 mm
PACKAGE WEIGHT 0.475g
Page 20 of
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Document Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM
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