Cypress STK14C88-3 manual Software Controlled STORE/RECALL Cycle

STK14C88-3

Software Controlled STORE/RECALL Cycle

The software controlled STORE/RECALL cycle follows. [18, 19]

	Parameter		Alt	Description		35 ns			45 ns		Unit
					Min		Max	Min		Max
tRC[16]		tAVAV		STORE/RECALL Initiation Cycle Time	35			45			ns
t	[18, 19]	t	AVEL	Address Setup Time	0			0			ns
	SA
tCW[18, 19]		tELEH		Clock Pulse Width	25			30			ns
tHACE[18, 19]		tELAX		Address Hold Time	20			20			ns
tRECALL				RECALL Duration			20			20	μs

Switching Waveforms

Figure 12. CE Controlled Software STORE/RECALL Cycle [19]

ADDRESS

CE

OE

DQ (DATA)

tRC

ADDRESS # 1

tSA tSCE

tHACE

DATA VALID

tRC

ADDRESS # 6

tSTORE / tRECALL

HIGH IMPEDANCE

DATA VALID

Notes

18.The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence).

19.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.

Document Number: 001-50592 Rev. ** Page 12 of 17

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