DDR DIMM timing register, which provides the DIMM speed control for the entire array, must be programmed to use the timings of the slowest DIMMs installed. Note: DIMMs must be populated in identical pairs for
BIOS: Award / Phoenix BIOS advanced by ADLINK
•
•Flash write protection will be implemented under software control. This bit must be set to 1 before any write will be allowed to the BIOS Flash.
Gigabit Ethernet
•One 10/100/1000Mbps Ethernet interfaces via the Intel® 82547GI Gigabit Ethernet Controller. The 82547GI is connected to the CSA (Communicating Streaming Architecture) interface of the 82875P MCH.
•Support
•IEEE802.3x compliant flow control, support
•Ethernet link status and activity LEDs on the
Graphic Display
•ATI Mobility M9 (AGP4X) or M10 (AGP8X) VGA chip with 64MB video memory.
•Standard SVGA CRT analog output on bracket I/O panel.
•Also supports 2nd CRT output (via one onboard
USB Interface
•Supports four USB 2.0 ports, two connectors (USB0 & USB1) on bracket and the others (USB2 & USB3) are routed to one onboard
IDE Ports
•Two IDE connectors support up to four drivers. Up to Ultra DMA 100 Mode.
Super I/O and WDT
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Introduction • 9