Fujitsu MHC2032AT, MHD2021AT, MHC2040AT, MHD2032AT manual Ultra DMA CRC rules

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5.5 Ultra DMA Feature Set

13)The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-.

14)The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK.

5.5.5Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

a)Both the host and the device shall have a 16-bit CRC calculation function.

b)Both the host and the device shall calculate a CRC value for each Ultra DMA burst.

c)The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred.

d)For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged.

e)At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD (15:0) with the negation of DMACK-.

f)The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous Ultra DMa burst in the same command. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

g)For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one. ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by re-issuing the command.

h)A host may send extra data words on the last Ultra DMA burst of a data out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded by the device.

i)The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.

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Contents MHC2032AT, MHC2040AT MHD2032AT, MHD2021AT Disk Drives Product ManualFor Safe Operation Handling of This ManualPage Revision History Page Preface Overview of ManualConventions for Alert Messages Operating EnvironmentLiability Exception Page Important Alert Items Important Alert MessagesPage Contents Contents Interface Contents GL-1 Illustrations FiguresTables Surface temperature measurement points and standard values Device Overview Functions and performance FeaturesAdaptability Features Device Specifications Specifications summarySpecifications MHC2032AT/MHC2040AT MHC2032AT MHC2040ATSpecifications MHD2021AT/MHD2032AT MHD2021AT MHD2032ATPower Requirements Model and product numberMHC2032AT MHD2021ATCurrent and power dissipation Current fluctuation Typ. at +5V when power is turned onEnvironmental Specifications Environmental specificationsAcoustic noise specification Acoustic NoiseShock and Vibration Error Rate Media DefectsDevice Configuration Device Configuration Disk drive outerview the MHC Series and MHD SeriesConfiguration of disk media heads ATA interface System Configuration2 1 drive connection 2 drives configuration 3 2 drives connectionPage Installation Conditions Dimensions Dimensions MHC series 1/2Dimensions MHD series 2/2 Mounting Orientation Sample MHC2040ATPCA Mounting frame structureMeasurement point Temperature Service area Sample MHC2040AT Device connector Cable ConnectionsCable connector specifications Cable connector specificationsDevice connection BergPower supply connector CN1 Jumper SettingsLocation of setting jumpers Factory default setting Master drive-slave drive setting12 Csel setting 13 Example 1 of Cable Select14 Example 2 of Cable Select Page Theory of Device Operation Outline SubassembliesDisk HeadActuator SpindleAir filter Circuit Configuration Circuit Configuration Power-on Sequence Self-calibration contents Self-calibrationExecution timing of self-calibration Command processing during self-calibration Self-calibration execution timechartRead/write Circuit Read/write preamplifier PreAMPWrite circuit Write precompensation algorithmRead/write circuit block diagram Frequency characteristic of programmable filter Read circuitDigital PLL circuit Servo Control Servo control circuitServo Control Physical sector servo configuration on disk surface Servo Control Data-surface servo format Servo frame formatActuator motor control Spindle motor control Servo Control Page Interface Interface signals Physical InterfaceSignal assignment on the interface connector Signal assignment on the connectorDasp GND Encsel DiowStop DiorIordy DaspDdmardy Logical Interface I/O registers 1 I/O registersDA2 DA1 DA0 Command block registers UNC Idnf AbrtLogical Interface DEV HS3 HS2 HS1 HS0 BSY DSC DRQ ERRInterface Control block registers Host CommandsSrst Command code and parameters Command code and parameters 1Command code and parameters 2 Command descriptions Host Commands Read Multiple X’C4’ Host Commands Execution example of Read Multiple command Host Commands Interface End head No. /LBA MSB 1F7 HCM 1F6 HDH Write Multiple X’C5’ Interface Write Verify X’3C’ Interface Host Commands Initialize Device Parameters X’91’ Identify Device X’EC’ Information to be read by Identify Device command 1 Number of current Cylinders Information to be read by Identify Device command 2 Command Bit Reserved Multiple sector transfer =Enable Information to be read by Identify Device command 3 Identify Device DMA X’EE’ SET Features X’EF’ Features register values and settable modes’AA’ ’BB’Host Commands SET Multiple Mode X’C6’ Host Commands Execute Device Diagnostic X’90’ Diagnostic code Interface Host Commands Write Buffer X’E8’ Host Commands Interface Host Commands Interface Host Commands ’FF’ Host Commands Features Register values subcommands and functions Features Resister Function Format of device attribute value data 1FFFormat of insurance failure threshold value data Interface Host Commands Interface 10 Contents of security password At command issuance I-O register contents 1F7 hCM Host Commands Read DMA Write DMA 11 Contents of Security SET Password data Locked Mode Flush Cache E7 Error posting 13 Command code and parameters 113 Command code and parameters 2 Data transferring commands from device to host Command ProtocolExecute Device Diagnostic Initialize Device Parameters Read Sectors command protocol Data transferring commands from host to device Protocol for command abortWrite Sectors command protocol Commands without data transfer DMA data transfer commands Other commandsRead Multiple Sleep Write Multiple Normal DMA data transfer Ultra DMA Feature Set OverviewPhases of operation Ultra DMA burst initiation phaseData transfer phase Ultra DMA burst termination phaseUltra DMA data in commands Initiating an Ultra DMA data in burstPausing an Ultra DMA data in burst Data in transferTerminating an Ultra DMA data in burst Ultra DMA Feature Set Interface Initiating an Ultra DMA data out burst Ultra DMA data out commandsData out transfer Pausing an Ultra DMA data out burst Terminating an Ultra DMA data out burst Interface Ultra DMA CRC rules XOR f11 Series termination required for Ultra DMA 15 Recommended series termination for Ultra DMATiming PIO data transfer10 Data transfer timing 11 Single word DMA data transfer timing mode Single word DMA data transfer12 Multiword DMA data transfer timing mode Multiword DMA data transferTransfer of Ultra DMA data Starting of Ultra DMA data In BurstName Mode Comment MIN MAX 16 Ultra DMA data burst timing requirements 2 DmardySustained Ultra DMA data in burst 14 Sustained Ultra DMA data in burstHost pausing an Ultra DMA data in burst 15 Host pausing an Ultra DMA data in burstDevice terminating an Ultra DMA data in burst 16 Device terminating an Ultra DMA data in burstHost terminating an Ultra DMA data in burst 17 Host terminating an Ultra DMA data in burst18 Initiating an Ultra DMA data out burst Sustained Ultra DMA data out burst 19 Sustained Ultra DMA data out burstDevice pausing an Ultra DMA data out burst 20 Device pausing an Ultra DMA data out burstHost terminating an Ultra DMA data out burst 21 Host terminating an Ultra DMA data out burst22 Device terminating an Ultra DMA data out burst Power-on and reset 23 Power on Reset TimingOperations Device Response to the Reset Response to power-onResponse to power-on Response to hardware reset Response to hardware resetResponse to software reset Response to software resetResponse to diagnostic command Response to diagnostic commandDefault parameters Default parametersAddress Translation Address translation example in CHS mode Logical addressPower Save Power save modeOperations Power commands Defect ManagementSpare area Alternating defective sectorsAlternate cylinder assignment Read-Ahead Cache Data buffer configurationCaching operation − Write Sectors − Write DMA − Write Multiple Read Sector S Read Multiple Read DMA− Read Sector S − Read DMA Usage of read segment Mis-hit no hitSequential read HAP DAPRead-ahead data New read-ahead data Hit data Full hit hit all Partially hit Write Cache Write Sectors Write Multiple Page Glossary Power save mode Rotational delayPIO Programmed input-output PositioningStatus VCMPage Acronyms and Abbreviations Page Index Index DACInitialize Device Parameters MPU Mtbf Mttr Read DMA Read Long 5-43 Read Multiple 5-18 Read SectorsSET Features IN-6 C141-E050-02EN Page Comment Form MHC2032AT, MHC2040AT, MHD2032AT, MHD2021AT DiskDrives Product Manual Japan

MHC2040AT, MHC2032AT, MHD2032AT, MHD2021AT specifications

Fujitsu offers a range of advanced hard disk drives (HDD) designed for various computing needs, including the MHD2021AT, MHD2032AT, MHC2032AT, and MHC2040AT models. These drives combine reliable performance, capacity options, and technological features aimed at enhancing data storage efficiency.

The Fujitsu MHD2021AT is known for its capacity of 20 GB, making it an excellent choice for users requiring a compact and efficient HDD. With a spindle speed of 5400 RPM, it balances speed and power consumption, catering to mobile computing and lower power devices. Its ATA interface ensures compatibility with a wide range of systems, making it a versatile option for various applications.

The MHD2032AT model offers a slightly higher capacity of 30 GB, maintaining similar technological attributes to its predecessor. With an enhanced data transfer rate, it allows for quicker access to stored files, perfect for users handling larger volumes of data. The robust error correction features in this model further ensure data integrity, making it a reliable choice for demanding environments.

For users needing more robust storage solutions, the MHC2032AT steps it up with features tailored for performance-heavy applications. Its 30 GB capacity is suited for desktop and workstation environments that require swift data retrieval and significant storage. The drive employs advanced caching techniques, which boost performance further by optimizing read and write operations, ensuring smoother multitasking capabilities.

The MHC2040AT is the flagship model in this line, providing an impressive storage capacity of 40 GB. This HDD is designed for high-performance applications where speed is crucial. The drive’s increased spindle speed and superior data transfer rates make it ideal for video editing, gaming, and large database management. Alongside its enhanced performance features, it includes advanced thermal management technology that maintains optimal operational temperatures, prolonging the drive's lifespan.

All four models leverage Fujitsu's commitment to data reliability, featuring robust shock resistance and low noise levels. Collectively, these drives cater to a spectrum of user needs, from compact data storage to high-capacity solutions, maintaining Fujitsu's reputation for quality and innovation in the storage market.
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