Cisco Systems Cisco 12404 CSF Functionality, Clock and Scheduler Functionality, System Clock

Appendix A Technical Specifications

Product Architecture

MBus Module Port Pin Assignments

Twenty general purpose pins and four analog input pins on the MBus module are used for this design.

CSF Functionality

The CSF circuity provides synchronized speed interconnections for the line cards and the RP (Figure A-5). The CSF circuitry consists of clock and scheduler, and switch fabric functionality; is contained on one card, housed in the bottom slot in the chassis. The CSF card has a switching capacity of 40 Gbps.

Figure A-5 CSF Card Slot

CLEAN	CLASS 1 LASER PRODUCT
	LASERPRODUKT DER KLASSE
	PRODUIT LASER DE CLASSE 11
	PRODUCTO LASER DE CLASSE 1	0

1 2 3

40C48/POS-SR-SC

	GIGABIT ROUTE
	PROCESSOR
CR
ITICMAJ M
AL	ORINOR

MBUS

FAIL

ENABLE

CONSOLIDATED SWITCH FABRIC

66293

Clock and Scheduler Functionality

The CSF card generates and distributes system-wide clock and cell time synchronization signaling. System clock generation is delivered to the system via the backplane and local clock functions are derived from the system clock.

System Clock

The system clock synchronizes data transfers between line cards or between the RP and a line card through the CSF. The system clock signal is sent to all line cards and the RP.

	Cisco 12404 Internet Router Installation and Configuration Guide
OL-11636-01		A-21