Texas Instruments TI SITARA manual AM3517/05 Core and Accelerators, Cores

AM3517/05 Core and Accelerators

Multi window overlay system and

resizing for hardware accelerated

￿￿￿￿￿￿￿￿

user interfaces

AM3517/05

￿ Cores

rocessors

ARM®

DisplayDisplay SubsystemSubsystem

￿ 600 MHz Cortex A-8 with NEON™

coprocessor

Cortex™-

3D

LCD

Video

10 bit DAC

Cont-

10 bit DAC

￿ PowerVR SGX 3D graphics

A8

Graphics

roller

Enc

Accelerator

Accelerator – up to 10M

(3517)

Video

16-bit Video

polygons / second

ProcessingProcessing

Front End

Input

Up to 1000 Dhrystone MIPS:

L3/

terconnect

• OS’s like Linux or WinCE

• Excellent web experience

CAN

HDQ /

Timer

USBSB HSHS HostHost x2x2

￿ Memory

EMAC

GP 2

1-wire

USB OTG

W

x1

￿ ARM:

w/PHY

I2C x3

￿ 16 kB I-Cache; 16 kB D-Cache;

McBSP x5

256kB L2 Cache

UART 3

DDR2

MMC/SD/

McSPI x4

￿ On chip: 64kB SRAM; 128kB

+1 w/I A

GPMC

SDIO x3

ROM

• Up to 10M polygons per second

￿ DDR2 interface

• Hardware based on screen display

￿ GPMC: NAND/NOR I/F

• Easily create robust GUI’s

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