Products Affected. A0, A2, A5, Sfence

Preliminary Information

24332E— December 2002

AMD Athlon™ Processor Model 6 Revision Guide

20 Processor Performance Counters Do Not Count Some x86 Instructions

Products Affected. A0, A2, A5

Normal Specified Operation. The processor should count all x86 instructions when programmed to do so.

Non-conformance.There are two types of uncounted instructions. One set of instructions is always uncounted. Another set of instructions are uncounted only if a certain data dependency exists.

Instructions never counted are: RDMSR, WRMSR, FSTENV, FSAVE, FLDENV, FPTAN, FYL2XP1, FCLEX, LLDT, LTR, MOV CRx, LGDT, LIDT, INVLPG, INVD, WBINVD, MOV DRx, CPUID, and

SFENCE.

Instructions that are uncounted only when certain data dependencies exist are:

■LAR, LSL, VERR, VERW if they clear the Zero Flag

■FXSAVE, FXRSTOR if FERR is changed

■FPU instructions with exceptional data conditions

■IO instructions that detect an interrupt

■POPF with the trap flag =1

■POPFD and PUSHFD with IOPL not equal 3 and Virtual Mode enabled

■POPFD when Alignment Check is being enabled

■MOV SS with the trap flag =1

■Segment Loads that generate accessed bit exceptions

■STI with the trap flag or the interrupt flag already a 1

■CLTS with the CR0.TS flag =1

■LMSW that changes any bit

Potential Effect on System. Performance counter may under count the actual number of x86 instructions.

Suggested Workaround. Versions of the AMD Athlon™ processor not affected by this erratum may be used to gather instruction counts.

Resolution Status. No fix planned.

6 specifications

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