Analog Devices AD620, C1599c07 specifications

Page 9

 

 

 

 

 

 

AD620

 

 

20

 

 

 

 

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15

 

 

 

 

 

 

 

TO 0.01%

 

 

 

ms

 

 

 

 

 

 

 

 

 

TO 0.1%

 

TIME

10

 

 

 

 

 

SETTLING

 

 

 

 

 

 

 

 

 

 

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5

 

 

 

 

 

 

 

 

 

 

 

 

0

5

10

15

20

 

 

0

OUTPUT STEP SIZE – Volts

Figure 26. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF

Figure 29. Settling Time vs. Step Size (G = 1)

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Figure 27. Large Signal Response and Settling Time, G = 1000 (0.5 mV = 0.01%)

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Figure 28. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF

 

1000

 

 

 

s

 

 

 

 

m

100

 

 

 

 

 

 

 

SETTLING TIME

10

 

 

 

 

1

 

 

 

 

1

10

100

1000

 

 

 

GAIN

 

Figure 30. Settling Time to 0.01% vs. Gain, for a 10 V Step

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Figure 31a. Gain Nonlinearity, G = 1, RL = 10 kΩ

(10 μV = 1 ppm)

REV. E

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Image 9
Contents Product Description Connection DiagramAD620-SPECIFICATIONS AD620 Absolute Maximum RATINGS1 Ordering GuideMetalization Photograph Typical Distribution of Input Offset Voltage AD620-Typical Characteristics Positive PSR vs. Frequency, RTI G = Output Voltage Swing vs. Load Resistance AD620 Theory of Operation AD620AD620A Pressure Measurement Input and Output Offset Voltage Gain SelectionReference Terminal Input ProtectionGrounding COMMON-MODE RejectionGround Returns for Bias Currents with Thermocouple Inputs Ground Returns for Input Bias CurrentsPlastic DIP N-8 Package Outline Dimensions