I INDEX
A
architecture, of this
B
bill of materials,
C
connectors,
D
dimensions, of this
E
expansion interface,
J
JP1 (processor select) jumper,
N
notation conventions,
P
parallel port,
printed circuit boards (PCBs),
S
schematic, of this
F | U | |
FLAG0 (USB reset) pin, | ||
USB | ||
processors, | ||
controller, | ||
FLAG1 (USB IRQ) pin, | ||
device memory map, | ||
processors, | ||
documentation, | ||
FLAG2 (USB reset) pin, | ||
IRQ line, | ||
processors, | ||
reset, | ||
| ||
I |
| |
interrupt request line (IRQ), |
|
SHARC USB |