Seagate 6450, 6451 manual Synchronous DMA Transfer Signal Line Definitions, Protocol Rules

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Medalist Pro 6450/6451 Product Manual, Rev. B

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You can disable both the Write Reallocation and write cache using value 82H. These two features coexists as a pair and are enabled/disabled together.

3.3 Synchronous DMA Transfer

3.3.1Signal Line Definitions

Some existing ATA signal lines are redefined during the Synchronous DMA protocol to provide new functions. If the Synchronous DMA transfer mode was previously chosen by the Set Features, the ATA lines change from the old to new definitions as soon as the host allows for a DMA burst. The drive detects this change when the –DMACK line is asserted. These lines revert back to their original definitions upon the de-assertions of –DMACK at the termination of the DMA burst.

Signal Line Definitions

New Definitions

Old Definitions

DMARQ

DMARQ

 

 

–DMACK

–DMACK

 

 

–DMACK

IORDY on write commands

 

–DIOR on read commands

 

 

STROBE

–DIOR on write commands

 

IORDY on read commands

STOP

–DIOW

Note. DMARQ and –DMACK signal lines remain unchanged. This en- sures backward-compatibility with PIO modes.

3.3.2Protocol Rules

The general rules of the Synchronous DMA Transfer Protocol are as follows:

∙A DMA burst is defined as the period from an assertion of –DMACK to subsequent de-assertion of –DMACK.

∙A receiver must be prepared to receive at least two words of data whenever it enters or resumes a burst mode.

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Contents Product Manual Page Product Manual Page Contents Appendix. Timing diagrams Configuring and mounting the driveATA interface Figures Medalist Pro 6450/6451 Product Manual, Rev. B Introduction Performance CapacityEnergy-efficiency Drive specification ST36450A ST36451A Quick specification chartVoltage tolerance including noise +12V Standard configuration SpecificationsFormatted capacity Physical organization Functional specificationsST36450A ST36451A Seek time Physical dimensionsMultisegmented cache buffer Start and stop times Typical power-up and power-down sequenceAuto-park Power-up sequencePower-down sequence Power specifications Power managementSleep mode Active modeIdle mode Standby modeEnvironmental specifications 1.13.1 Ambient temperature Power consumptionInput noise Shock and vibration Temperature gradientAltitude Relative humidityAgency listings Overall A-weighted Value IdleAcoustics ReliabilityFCC verification Electromagnetic Compliance for the European UnionPage Sicherheitsanleitung Handling and static-discharge precautions Configuring and mounting the drivePart Description Part number I/O cable and connectorPower connector Part DescriptionOptions jumper block ConnectorsConfiguration Settings Master/slave configurationCable-select option Alternate capacity jumperRemote LED connection Mounting the drive Connecting cable-selected drivesMounting dimensions Medalist Pro 6450/6451 Product Manual, Rev. B ATA Interface ATA Interface connector pin assignmentsATA interface connector pin assignments Command name Parameters used Command setCA, CB Word Description Value Identify drive command ECHWord Description Value Word Description Value Feature Value Set Features command EFHUpper 5 bits PIO and DMA Data-Transfer ModesAutomatic Reallocation Standby timer timeout periodSleep command 99H, E6H Sector Count Register contents Corresponding timeout periodSignal Line Definitions New Definitions Old Definitions Synchronous DMA Transfer Signal Line DefinitionsProtocol Rules Field/Bit Description Error RegisterTime Description Min Max Appendix. Timing diagramsProgrammed I/O timing with Iordy TKR Sustained Synchronous DMA burst Time Description ModePage Page

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