Appendix A Specifications
A.1 Digital Input/Output
Channels | 48 |
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Programming | 8255 PPI Mode0 |
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Mode |
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Input Voltage |
| Low | 0.8 V max |
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High | 2.0 V min |
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Output Voltage |
| Low | 0.5 V max. @ 12mA (sink) |
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High | 3.8 V min. @ |
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| 3.8 V min.@5mA(source)(high of every line) |
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+5V Output | 100mA | max. |
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Interrupt Mode | PC0 source; PC4 gate/PC0 source |
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A.2 Counter |
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Channels |
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| 2 independent |
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Resolution |
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Compatibility |
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| TTL compatible logical level input |
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Base Clock |
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| External |
| 8MHz max. | 2 independent program- |
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| mable clock sources |
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| Internal |
| 20MHz max. |
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Frequency |
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| Input frequency from 0.1Hz to 10Mhz |
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measurement |
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PWM Generation |
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| 2Hz to 10Mhz |
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External Input Divide |
| 2 to 65535 |
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A.3 General |
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I/O Connector Type |
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Dimensions | 132 X 80 X 32 mm (5.2” X 3.2” X 1.3”) |
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Power | 5 V @ 500 mA max. |
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Consumption |
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Temperature | Operation |
| 0~60° C (32~140° F) (refer to IEC |
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| Storage |
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Relative Humidity | 5%~95% RH |
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