EVGA 730a manual ‰ Timing Mode, ‰ DCTs Mode, ‰ CKE Base Power Down Mode, ‰ CKE Base Powerdown

Š(Trrd) RAS to RAS Delay: RAS#-to-RAS# delay of different banks (options are Auto, 2 through 5).

ŠTwtr command Delay: This is the minimum write-to-read delay with the same chip selected (options are Auto, 1 through 3).

ŠTrfc x for DIMMx: This is the minimum time from an auto-refresh command to an activate command or another auto refresh command. The recommended programming of this register varies based on DRAM density and speed. (options are Auto, 75ns, 105ns, 127.5ns, 195ns, 327.5ns).

‰Timing Mode

This item allows you to select the Timing Mode. The options are Auto, MaxMemClk and Manaul.

‰DCTs Mode

This item allows you to select the DCTs Mode. The options are Ganged (One 128bit channel) and Unganged (Dual 64bit independent channel).

‰CKE Base Power Down Mode

When in power down mode, if all pages of the DRAMs associated with a CKE pin are closed, then these parts are placed in power down mode. Only pre-charge power down mode is supported, not active power down mode. The Options are Enabled and Disabled.

‰CKE Base Powerdown

This bit is initialized based on the type of system being implemented. For non mobile systems, power down mode should be set to channel CKE control. The options are Per channel, Per CS.

‰Memclock tri-stating

Enables the DDR memory clocks to be tristated when alternate VID mode is enabled. The options are Enabled, Disabled.

‰Memory Hole Remapping

Enables to support 4G Memory Size. Options are Enabled, Disabled.

‰Auto Optimize Bottom IO

This item sets auto optimize maximal DRAM size when kernel assign PCI resources done. Options are Enabled, Disabled.