Measurement Specialties PCI-CTR05 manual Counter specifications

Page 17

PCI-CTR05 User's Guide

Specifications

Counter

Refer to the CTS9513-2 data sheet for complete 9513 specifications and operating modes. The SAVE command for the CTS9513 device does not behave predictably when using clocks which are not synchronous with the logic timing. The CTS9513-2 data sheet is available on our web site at www.mccdaq.com/PDFmanuals/9513A.pdf.

 

Table 4-3. Counter specifications

 

 

 

Parameter

 

Conditions

 

 

 

Counter type

 

9513

Configuration

 

One 9513 device. Five up/down counters, 16 bits each.

Compatibility

 

5V/TTL

The 9513 device is programmable for:

 

Clock source

 

Software selectable:

 

 

External:

 

 

ƒ

Counter 1-5 clock inputs

 

 

ƒ

Counter 1-5 gate inputs

 

 

Internal:

 

 

ƒ

Terminal count of previous counter

 

 

ƒ

X2 clock frequency scaler

Gate:

 

Software selectable source:

 

 

External (default logic high):

 

 

ƒ

Active high or low level or edge, counter 1 – 5 gate input

 

 

ƒ

Active high level previous gate or next gate

 

 

ƒ

All external gate signals (CTRxGATE) individually pulled up

 

 

 

through 10K resistors to +5V.

 

 

Internal:

 

 

ƒ

Active high previous counter terminal count

 

 

ƒ

No gating.

Output:

 

Software selectable:

 

 

ƒ

Always low

 

 

ƒ

High pulse on terminal count

 

 

ƒ

Low pulse on terminal count

 

 

ƒ

Toggle on terminal count

 

 

ƒ

Inactive, high impedance at user connector counter # output.

Osc Out

 

Software selectable source:

 

 

ƒ

Counter # input

 

 

ƒ

Gate # input

 

 

ƒ

Prescaled clock source (X2 clock frequency scaler)

 

 

Software selectable divider:

 

 

ƒ

Division by 1-16

 

 

Software selectable enable:

 

 

ƒ

On or low impedance to ground.

Clock input frequency

 

6.8 MHz max (145 nS min period)

X2 clock input sources

 

Software selectable:

 

 

ƒ

1.0 MHz (10 MHz Xtal divided by 10)

 

 

ƒ

5.0 MHz (10 MHz Xtal divided by 2)

 

 

ƒ

3.3 MHz (33 MHz PCI clock divided by 10)

 

 

ƒ

1.67 MHz (33 MHz PCI clock divided by 20)

X2 clock frequency scaler

 

BCD scaling (X2 divided by 10, 100, 1000 or 10000) or Binary scaling

 

 

(X2 divided by 16, 256, 4096 or 65536)

High pulse width (clock input)

 

70 ns min

Low pulse width (clock input)

 

70 ns min

Gate width high

 

145 ns min

Gate width low

 

145 ns min

4-2

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Contents Page PCI-CTR05 Management committed to your satisfaction Trademark and Copyright Information Table of Contents What you will learn from this users guide About this Users GuidePreface Conventions in this users guideWhere to find more information Chapter Software featuresIntroducing the PCI-CTR05 PCI-CTR05 functional block diagram Block diagramWhat comes with your PCI-CTR05 shipment? Installing the PCI-CTR05Hardware SoftwareUnpacking the board Installing the softwareOptional components C37FF-xC37FFS-xConnecting the board for I/O operations Installing the hardwareConnectors, cables main I/O connector Board connectors, cables, accessory equipmentRed stripe Identifies pin # C37FFS-x cable Field wiring, signal termination and conditioningRegister-level programming Programming and software applicationsProgramming languages Packaged application programs Digital I/O specifications SpecificationsInterrupt specifications Digital input / outputCounter Counter specificationsMain connector and pin out Power consumptionEnvironmental MechanicalPin Signal Name Main connector J1 pin outEC Declaration of Conformity Mailinfo@mccdaq.com