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3 | ECHO | RO | Indicates the |
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2 | SPR | RO | Indicates the |
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1 | DIAG | RO | Indicates the |
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0 | STAT | RO | Indicates the |
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| ||
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| ||
| Low PCI SN command address register (32 bits, R/W) | ||
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Bit # | Name | Type | Description |
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NA | R/W | This register is used to establish the low | |
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| address for SN commands to the |
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| of the bottom |
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| three bits hardwired to zeroes. Transfers must begin on a |
|
|
| Double DWORD |
Reserved | RO | These bits are reserved (must be written with zeroes). | |
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|
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|
| ||
| High PCI SN command address register (32 bits, R/W) | ||
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Bit # | Name | Type | Description |
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|
NA | R/W | Upper bits of this register are not used. | |
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|
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|
|
Low PCI SN response address register (32 bits, R/W)
Bit # | Name | Type | Description |
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|
NA | R/W | This register is used to establish the low | |
|
|
| address for SN responses from the |
|
|
| consists of the bottom |
|
|
| order three bits hardwired to zeroes. Transfers must begin |
|
|
| on a Double DWORD |
Reserved | RO | These bits are reserved (must be written with zeroes). | |
|
|
|
|
High PCI SN response address register (32 bits, R/W)
Bit # | Name | Type | Description |
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|
|
|
NA | R/W | Upper bits of this register are not used. | |
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PCI200 User Guide | Texas Memory Systems, Inc. (8/6/01) |