SOYO SY-7VCA user manual PCI Delay Transaction, PCI#2 Access #1 Retry, AGP Master 1 WS Write

BIOS Setup UtilitySY-7VCA

CHIPSET FEATURES SETUP (Continued)

CHIPSET	Setting	Description	Note
FEATURES

PCI Delay Transaction

Disabled

Enabled

The chipset has an embedded 32-bit posted write buffer to support delay Default transactions cycles. Select Enabled

to support compliance with PCI specification version 2.1.

PCI#2 Access #1 Retry

Disabled

Enabled

When disabled, PCI#2 will not be

disconnected until access finishes Default (difault). When enabled, PCI#2 will

be disconnected if max retries are attempted without success.

AGP Master 1 WS Write

Disabled		Default
Enabled	When Enabled, writes to the
	AGP(Accelerated Graphics Port) are
	executed with one wait states.

AGP Master 1 WS Read

Disabled		Default
Enabled	When Enabled, read to the AGP
	(Accelerated Graphics Port) are
	executed with one wait states.

Memory

Parity/ECC

Check

Disabled		Default
Enabled	This item enabled to detect the
	memory parity and Error Checking
	& Correcting.

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