Clevo M760TU, M740TU manual Sheet 4 Penryn Socket-P CPU 2/2, I D 4 4 I D 5 4, 5V S

Penryn (Socket-P) CPU 2/2

PLACE NEAR CPU

V C ORE

Schematic Diagrams

V CO RE

A 7

A 9

A 1 0

A 1 2

A 1 3

A 1 5

A 1 7

A 1 8

A 2 0

B 7

B 9

B 1 0

B 1 2

B 1 4

B 1 5

B 1 7

B 1 8

B 2 0

C9

C1 0

C1 2

C1 3

C1 5

C1 7

C1 8

D9

D1 0

D1 2

D1 4

D1 5

D1 7

D1 8

E 7

E 9

E 1 0

E 1 2

E 1 3

E 1 5

E 1 7

E 1 8

E 2 0

F 7

F 9

F 1 0

F 1 2

F 1 4

F 1 5

F 1 7

F 1 8

F 2 0

A A 7

A A 9

A A 1 0

A A 1 2

A A 1 3

A A 1 5

A A 1 7

A A 1 8

A A 2 0

A B 9

A C1 0

A B 1 0

A B 1 2

A B 1 4

A B 1 5

A B 1 7

A B 1 8

U 2 2C

V C C[0 0 1]	V CC [0 68 ]
V C C[0 0 2]	V CC [0 69 ]
V C C[0 0 3]	V CC [0 70 ]
V C C[0 0 4]	V CC [0 71 ]
V C C[0 0 5]	V CC [0 72 ]
V C C[0 0 6]	V CC [0 73 ]
V C C[0 0 7]	V CC [0 74 ]
V C C[0 0 8]	V CC [0 75 ]
V C C[0 0 9]	V CC [0 76 ]
V C C[0 1 0]	V CC [0 77 ]
V C C[0 1 1]	V CC [0 78 ]
V C C[0 1 2]	V CC [0 79 ]
V C C[0 1 3]	V CC [0 80 ]
V C C[0 1 4]	V CC [0 81 ]
V C C[0 1 5]	V CC [0 82 ]
V C C[0 1 6]	V CC [0 83 ]
V C C[0 1 7]	V CC [0 84 ]
V C C[0 1 8]	V CC [0 85 ]
V C C[0 1 9]	V CC [0 86 ]
V C C[0 2 0]	V CC [0 87 ]
V C C[0 2 1]	V CC [0 88 ]
V C C[0 2 2]	V CC [0 89 ]
V C C[0 2 3]	V CC [0 90 ]
V C C[0 2 4]	V CC [0 91 ]
V C C[0 2 5]	V CC [0 92 ]
V C C[0 2 6]	V CC [0 93 ]
V C C[0 2 7]	V CC [0 94 ]
V C C[0 2 8]	V CC [0 95 ]
V C C[0 2 9]	V CC [0 96 ]
V C C[0 3 0]	V CC [0 97 ]
V C C[0 3 1]	V CC [0 98 ]
V C C[0 3 2]	V CC [0 99 ]
V C C[0 3 3]	V CC [1 00 ]
V C C[0 3 4]
V C C[0 3 5]	V	CCP	[01	]
V C C[0 3 6]	V	CCP	[02	]
V C C[0 3 7]	V	CCP	[03	]
V C C[0 3 8]	V	CCP	[04	]
V C C[0 3 9]	V	CCP	[05	]
V C C[0 4 0]	V	CCP	[06	]
V C C[0 4 1]	V	CCP	[07	]
V C C[0 4 2]	V	CCP	[08	]
V C C[0 4 3]	V	CCP	[09	]
V C C[0 4 4]	V	CCP	[10	]
V C C[0 4 5]	V	CCP	[11	]
V C C[0 4 6]	V	CCP	[12	]
V C C[0 4 7]	V	CCP	[13	]
V C C[0 4 8]	V	CCP	[14	]
V C C[0 4 9]	V	CCP	[15	]
V C C[0 5 0]	V	CCP	[16	]
V C C[0 5 1]	V	CCA	[01	]
V C C[0 5 2]
V C C[0 5 3]	V	CCA	[02	]
V C C[0 5 4]
V C C[0 5 5]		V ID[0 ]
V C C[0 5 6]		V ID[1 ]
V C C[0 5 7]		V ID[2 ]
V C C[0 5 8]		V ID[3 ]
V C C[0 5 9]		V ID[4 ]
V C C[0 6 0]		V ID[5 ]
V C C[0 6 1]		V ID[6 ]
V C C[0 6 2]
V C C[0 6 3]	V C CS E NS E
V C C[0 6 4]
V C C[0 6 5]
V C C[0 6 6]
V C C[0 6 7]	V S S S E NS E

P en ry n

V C OR E

A B 20

AB 7 A C7

A C9

A C1 2

AC1 3 A C1 5

AC1 7 A C1 8

A D7

A D9

AD1 0 A D1 2

AD1 4 A D1 5

AD1 7 A D1 8

AE 9 A E 10

A

E 12

A

E 13

A

E 15

A

E 17

A

E 18

A

E 20

A

F 9

A

F 10

A

F 12

A

F 14

A

F 15

A

F 17

A

F 18

A

F 20

80mils

G

2 1

1 . 0 5V S

V

6

J 6

K

6

M

6

J 2 1

K

21

M

2 1

N

2 1

N

6

1 . 5 V S

Layout note:

R

2 1

20mils

R

6

T 2 1

PL AC E

AS

C LOS E

T 6

C6 4 5

C6 5 3

AS

P OS SI BL E T O

V

21

W

21

TH E CP U

VC CA PI N

B

26

10 U _ 1 0 V _ 08

. 0 1 U _ 5 0V _ X 7 R _ 0 4

C

2 6

A

D6

H _ V ID0

4 1

A

F 5

H _ V ID1

4 1

TO POWER

PAGE

A

E 5

H _ V ID2

4 1

A

F 4

H _ V ID3

4 1

A

E 3

H _ V I D 4 4 1

A

F 3

A

E 2

H _ V I D 5 4 1

H _ V ID6

4 1

A F 7

V C C S E N S E

V C C S E N S E

41

A E 7

V S S S E NS E

V S S S E N S E

4 1

.

R1 4

R1 3

Layout note:

1 00 _ 1 %_ 0 6

Rou te V CC SEN SE

a nd

1 0 0_ 1 % _ 06

VSS SE NS E

tra ce s

at

2 7.4 Oh m

V COR E

wit h

50

m il

sp ac in g.

Pla ce P U

and

P D

wi th in 1

inc h

of

C PU.

A 4

A 8

A 11

A 14 A 16

A 19 A 23

A F 2 B 6

B 8

B 11

B 13 B 16

B 19 B 21

B 24 C5

C8 C 11

C14 C 16

C19

C2

C22 C 25

D1

D4

D8

D11 D 13

D16 D 19

D23 D 26

E 3

E 6

E 8

E 11

E 14 E 16

E 19 E 21

E 24 F 5

F 8 F 11

F 13 F 16

F 19 F 2

F 22 F 25

G4

G1

G23 G 26

H3

H6

H21 H 24

J2

J5

J22

J25

K 1 K 4 K 23

K 26 L3 L6

L21

L24

M2

M5

M22

M25

N1

N4

N23

N26 P 3

U 2 2	D
V S	S [00 1 ]	V S S [	08 2 ]
V S	S [00 2 ]	V S S [	08 3 ]
V S	S [00 3 ]	V S S [	08 4 ]
V S	S [00 4 ]	V S S [	08 5 ]
V S	S [00 5 ]	V S S [	08 6 ]
V S	S [00 6 ]	V S S [	08 7 ]
V S	S [00 7 ]	V S S [	08 8 ]
V S	S [00 8 ]	V S S [	08 9 ]
V S	S [00 9 ]	V S S [	09 0 ]
V S	S [01 0 ]	V S S [	09 1 ]
V S	S [01 1 ]	V S S [	09 2 ]
V S	S [01 2 ]	V S S [	09 3 ]
V S	S [01 3 ]	V S S [	09 4 ]
V S	S [01 4 ]	V S S [	09 5 ]
V S	S [01 5 ]	V S S [	09 6 ]
V S	S [01 6 ]	V S S [	09 7 ]
V S	S [01 7 ]	V S S [	09 8 ]
V S	S [01 8 ]	V S S [	09 9 ]
V S	S [01 9 ]	V S S [	10 0 ]
V S	S [02 0 ]	V S S [	10 1 ]
V S	S [02 1 ]	V S S [	10 2 ]
V S	S [02 2 ]	V S S [	10 3 ]
V S	S [02 3 ]	V S S [	10 4 ]
V S	S [02 4 ]	V S S [	10 5 ]
V S	S [02 5 ]	V S S [	10 6 ]
V S	S [02 6 ]	V S S [	10 7 ]
V S	S [02 7 ]	V S S [	10 8 ]
V S	S [02 8 ]	V S S [	10 9 ]
V S	S [02 9 ]	V S S [	11 0 ]
V S	S [03 0 ]	V S S [	11 1 ]
V S	S [03 1 ]	V S S [	11 2 ]
V S	S [03 2 ]	V S S [	11 3 ]
V S	S [03 3 ]	V S S [	11 4 ]
V S	S [03 4 ]	V S S [	11 5 ]
V S	S [03 5 ]	V S S [	11 6 ]
V S	S [03 6 ]	V S S [	11 7 ]
V S	S [03 7 ]	V S S [	11 8 ]
V S	S [03 8 ]	V S S [	11 9 ]
V S	S [03 9 ]	V S S [	12 0 ]
V S	S [04 0 ]	V S S [	12 1 ]
V S	S [04 1 ]	V S S [	12 2 ]
V S	S [04 2 ]	V S S [	12 3 ]
V S	S [04 3 ]	V S S [	12 4 ]
V S	S [04 4 ]	V S S [	12 5 ]
V S	S [04 5 ]	V S S [	12 6 ]
V S	S [04 6 ]	V S S [	12 7 ]
V S	S [04 7 ]	V S S [	12 8 ]
V S	S [04 8 ]	V S S [	12 9 ]
V S	S [04 9 ]	V S S [	13 0 ]
V S	S [05 0 ]	V S S [	13 1 ]
V S	S [05 1 ]	V S S [	13 2 ]
V S	S [05 2 ]	V S S [	13 3 ]
V S	S [05 3 ]	V S S [	13 4 ]
V S	S [05 4 ]	V S S [	13 5 ]
V S	S [05 5 ]	V S S [	13 6 ]
V S	S [05 6 ]	V S S [	13 7 ]
V S	S [05 7 ]	V S S [	13 8 ]
V S	S [05 8 ]	V S S [	13 9 ]
V S	S [05 9 ]	V S S [	14 0 ]
V S	S [06 0 ]	V S S [	14 1 ]
V S	S [06 1 ]	V S S [	14 2 ]
V S	S [06 2 ]	V S S [	14 3 ]
V S	S [06 3 ]	V S S [	14 4 ]
V S	S [06 4 ]	V S S [	14 5 ]
V S	S [06 5 ]	V S S [	14 6 ]
V S	S [06 6 ]	V S S [	14 7 ]
V S	S [06 7 ]	V S S [	14 8 ]
V S	S [06 8 ]	V S S [	14 9 ]
V S	S [06 9 ]	V S S [	15 0 ]
V S	S [07 0 ]	V S S [	15 1 ]
V S	S [07 1 ]	V S S [	15 2 ]
V S	S [07 2 ]	V S S [	15 3 ]
V S	S [07 3 ]	V S S [	15 4 ]
V S	S [07 4 ]	V S S [	15 5 ]
V S	S [07 5 ]	V S S [	15 6 ]
V S	S [07 6 ]	V S S [	15 7 ]
V S	S [07 7 ]	V S S [	15 8 ]
V S	S [07 8 ]	V S S [	15 9 ]
V S	S [07 9 ]	V S S [	16 0 ]
V S	S [08 0 ]	V S S [	16 1 ]
V S	S [08 1 ]	V S S [	16 2 ]
		V S S [	16 3 ]
P en ry n

P 6

C 20 7

C 2 0 9

C 68 1

C6 4 3

C 21 0

C 6 8 2

C 60 9

C 6 2 0

C 20 8

C 8 7

P 2 1

1 0 U _ 1 0V _ 0 8

10 U _1 0 V _ 08

1 0 U _ 1 0V _ 0 8

10 U _1 0 V _ 0 8

1 0 U _ 1 0V _0 8

10 U _1 0 V _ 0 8

* 10 U _1 0 V _ 08

*1 0 U _ 1 0V _ 0 8

* 10 U _1 0 V _ 08

*1 0 U _ 1 0V _0 8

P 2

4

R 2

R 5

V C OR E

R 22

R 25

T 1

T 4

T 2 3

C 13 4

C6 0 8

C 13 3

C8 6

T 2

6

U 3

2 2 U _ 6 . 3V _ 0 8

22 U _6 . 3 V _ 0 8

2 2 U _ 6 . 3V _0 8

22 U _6 . 3 V _ 0 8

U 6

U 21

U 24

V 2

V 5

C 64 4

C1 3 5

C 61 8

C8 8

C 61 9

V 2

2

V 2 5

2 2 U _ 6. 3V _ 0 8

22 U _6 . 3 V _ 0 8

2 2 U _ 6 . 3V _0 8

22 U _6 . 3 V _ 0 8

2 2 U _ 6 . 3V _0 8

W 1

W 4

W 2

3

W 2

6

V C OR E

Y 3

Y 6

Y

21

Y

24

A A 2

C 54

C 6 1 5

C 10 4

C6 2 3

C 19 1

C 8 9

A A

5

1U _ 6. 3 V _ 0 4

A A 8

1 U _ 6 . 3 V _0 4

1U _ 6. 3 V _ 0 4

1 U _ 6 . 3 V _ 04

1 U _ 6 . 3 V _ 04

1U _ 6. 3 V _ 0 4

A A

1

1

A A

1

4

A A

1

6

A A

1

9

V C OR E

A A

2

2

A A

2

5

A B

1

A B 4

C 19 0

C 1 0 5

C 19 2

C1 9 3

C 51

C1 9 4

A B

8

A B 1 1

1 U _ 6 . 3 V _0 4

1U _ 6. 3 V _ 0 4

1 U _ 6 . 3 V _ 04

1U _ 6. 3 V _ 0 4

1 U _ 6 . 3 V _ 04

1U _ 6. 3 V _ 0 4

A B

1

3

A B

1

6

A B

1

9

A B

2

3

V C ORE

A B

2

6

A C

3

A C

6

A C 8

C 52

C 18 9

C 6 0 5

C 63 9

C 6 2 1

C 53

A C

11

. 1 U _ 1 0 V _ X7 R _ 0 4

. 0 1 U _ 5 0 V _X 7 R _ 0 4

A C 14

. 0 1 U _ 5 0V _ X 7 R _ 0 4

. 1U _ 10 V _ X 7 R _ 0 4

. 1 U _ 1 0 V _ X7 R _0 4

. 1 U _ 10 V _ X 7 R _ 0 4

A C

16

A C

19

A C

21

A C

24

A D

2

A D

5

A D

8

A D

11

A D

13

A D

16

A D

19

NEAR CPU PIN

A D

22

1 . 0 5V S

A D

25

EMI

A E

1

A E

4

A E

8

A E 1 1

+C 62 7

C 11 3

C1 2 1

C 10 3

C 1 2 7

C 11 7

C 1 0 2

A E

1

4

A E 1 6

1 5 0U _ 4V _ B 2

. 1 U _ 1 0 V _ X7 R _ 0 4

. 1 U _ 10 V _ X 7 R _ 0 4

. 1 U _ 1 0 V _ X7 R _0 4

. 1 U _ 1 0V _ X 7 R _ 0 4

. 1 U _1 0 V _ X7 R _0 4

. 1 U _ 1 0V _ X 7 R _ 0 4

A E

1

9

A E

2

3

0.1UF*6 INSIDE CPU CENTER CAVITY IN 2 ROWS

A E

2

6

A 2

A F 6

A F 8

1 . 0 5V S

A F 1 1

A F 1 3

A F 1 6

A F 1 9

C 95

C 12 0

C 1 0 6

C 13 0

C1 2 2

A F 2 1

*. 1 U _ 1 0 V _ X7 R _ 0 4

A 2 5

* . 1U _ 10 V _ X 7R _ 04

* . 1U _ 10 V _ X 7R _ 04

*. 1 U _ 1 0 V _X 7 R _ 0 4

* . 1U _ 10 V _ X 7R _ 04

A F 2 5

. +VCCP = 1.05V (0.997V~1.102V)

10 ,2 2 ,23 ,2	5	,2	6,2 7 ,3 2,3	5	1 . 5	V S
2 ,3 ,5 ,7,9 ,1	0	,2	2,2 5 ,3 7,3	9	1 . 0	5V S
			4	1	V C	OR E

Sheet 4 of 51

Penryn (Socket-P)

CPU 2/2

B.Schematic Diagrams

Penryn (Socket-P) CPU 2/2 B - 5