DEC should read as follows | Motorola MPC750 instruction

MPC750UMAD/AD

1/1999 Rev. 1

Errata to

MPC750 RISC Microprocessor UserÕs Manual

This errata describes corrections to the MPC750 RISC Microprocessor UserÕs Manual. These corrections also apply to the MPC740, which is described in MPC750 RISC Microprocessor UserÕs Manual. For convenience, the section number and page number of the errata item in the userÕs manual are provided.

To locate any published updates for this document, refer to the world-wide web at http://www.mot.com/powerpc.

Section/Page	Changes
2.1.1, 2-7	The implementation note for the decrementer register
	(DEC) should read as follows:
	In the MPC750 the decrementer register is decremented
	and the time base is incremented at a speed that is
	one-fourth the speed of the bus clock.
2.1.2.2, 2-12	In Table 2-4, replace the description of HID0[DBP]
	(bit 1), with the following:

This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice.

MPC750 specifications

The Motorola MPC750 is a PowerPC microprocessor that was part of the PowerPC G3 family. Released in the late 1990s, it marked a significant advancement in the realm of computing performance and efficiency. Known for its robust design and versatility, the MPC750 was used in a variety of systems, from personal computers to embedded applications.

One of the standout features of the MPC750 is its implementation of the RISC (Reduced Instruction Set Computing) architecture, which enhances performance by optimizing the instruction set used in processing tasks. The processor operates with a reduced number of cycles per instruction, leading to faster execution and improved overall system efficiency. The MPC750 was built on a 0.25-micron process technology, which contributed to its compact size and lower power consumption compared to its predecessors.

The MPC750 supports clock speeds ranging from 200 MHz to 400 MHz, allowing it to cater to a range of applications where performance is paramount. This flexibility made it an appealing choice for manufacturers looking to create high-performance computing solutions. The architecture includes a high-bandwidth on-chip cache system, featuring both L1 and L2 caches. The L1 cache typically includes both data and instruction caches, while the L2 cache provides additional memory bandwidth, crucial for applications that require fast data processing.

In addition to its core processing capabilities, the MPC750 incorporates several advanced technologies, including SIMD (Single Instruction, Multiple Data) processing capabilities. This allows it to handle multiple data points with a single instruction, boosting performance in multimedia applications and data-intensive tasks. The processor also supports a variety of interfaces, making it versatile for integration into various systems.

Thermal management is another key characteristic of the MPC750. It was designed to operate efficiently at lower power levels, reducing heat generation, which is vital for maintaining system stability. This is particularly important in applications such as embedded systems where space constraints may limit cooling solutions.

Overall, the Motorola MPC750 microprocessor symbolizes a blend of performance, efficiency, and adaptability. Its combination of advanced technologies, support for RISC architecture, and features such as high-speed cache and SIMD processing made it a cornerstone of the PowerPC family and a preferred choice for developers during its time. As such, the MPC750 played a crucial role in the evolution of computing technology in the late 1990s and early 2000s.

MPC750 RISC Microprocessor UserÕs Manual

The implementation note for the decrementer register

(DEC) should read as follows:

and the time base is incremented at a speed that is

one-fourth the speed of the bus clock.

MPC750 specifications