Samsung S3F84B8 manual Internal Resource Arrangement and Configuration, Opa

S3F84B8_ALL-IN-ONE IH COOKER_AN_REV 0.00 3 SOFTWARE IMPLEMENTATION

3.3 INTERNAL RESOURCE ARRANGEMENT AND CONFIGURATION

Table 3-1 shows the internal resource arrangement and configuration.

Table 3-1 Internal Resource Arrangement and Configuration

Module		Purpose	Configuration	Registers
CMP0	Synchronization		Non-inverting output	CMP0CON
			Disable INT	CMPINT
				P1CON
CMP2	Surge protection		0.50VDD reference	CMP1CON
			Non-inverting output	CMPINT
			Enable INT	P1CON
CMP1	IGBT over-V protection		0.65VDD reference,	CMP2CON
			Non-inverting output,	CMPINT
			Enable INT	P1CON
OPA	Current amplification		On-chip mode	OPACON
				P2CONL
PWM	IGBT control		Co-operate with CMP0	PWMCON
			Delay Trigger	PWMCCON
			AMT Trigger	PWMDATAH/L
				PWMPDATAH/L
				P0CONH
BUZ	BUZ control		1KHz output	BUZCON
				P0CONL
TA	100ms timing for		Internal mode	TAPS
	1)	BUZ beaming time (0.2sec for every enable)	Match Interrupt Enable	TACON
	2)	Display blink interval (0.5sec)	TA Internal Clock = Fosc/4096
	3)	Error warning (BUZ) after error lasts for 2sec
	4)	Pan-on detect every 2sec
	5)	Move pan detect every 1.5sec
	6)	Power adjust every 0.1sec
	7)	Check sensor status after 3min of heating up
TC	Pulse counting for pan detection		Interval mode	TCCON
			Interrupt Disable	TCPS
			TC clock = CMP0_O

Table 3-1 shows the internal resource arrangement for IH cooker system and related registers in S3F84B8. For detail description of all the registers and co-operation ways of comparators and IH PWM, refer to the S3F84B8 user’s manual.

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