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Fujitsu CM71-00101-5E Instruction Manual
314 pages 5.35 Mb
5 PREFACE9 CONTENTS15 Main changes in this edition55 CHAPTER 4 RESET AND "EIT" PROCESSING91 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS96 7.1 ADD (Add Word Data of Source Register to Destination Instruction bit pattern : 1010 0110 0010 0011 97 7.2 ADD (Add 4-bit Immediate Data to Destination Register)Instruction bit pattern : 1010 0100 0010 0011 98 7.3 ADD2 (Add 4-bit Immediate Data to Destination Register)Instruction bit pattern : 1010 0101 1110 0011 99 7.4 ADDC (Add Word Data of Source Register and Carry Bit to Instruction bit pattern : 1010 0111 0010 0011 100 7.5 ADDN (Add Word Data of Source Register to Destination Instruction bit pattern : 1010 0010 0010 0011 101 7.6 ADDN (Add Immediate Data to Destination Register)Instruction bit pattern : 102 7.7 ADDN2 (Add Immediate Data to Destination Register)Instruction bit pattern :1010 0001 1110 0011 103 7.8 SUB (Subtract Word Data in Source Register from Instruction bit pattern : 1010 1100 0010 0011 104 7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)Subtracts the word data in "Rj" and the carry bit from the word data in "Ri", stores Instruction bit pattern : 1010 1101 0010 0011 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) 105 7.10 SUBN (Subtract Word Data in Source Register from Instruction bit pattern : 1010 1110 0010 0011 106 7.11 CMP (Compare Word Data in Source Register and Instruction bit pattern : 1010 1010 0010 0011 107 7.12 CMP (Compare Immediate Data of Source Register and Instruction bit pattern : 108 7.13 CMP2 (Compare Immediate Data and Destination Register)Instruction bit pattern : 109 7.14 AND (And Word Data of Source Register to Destination Takes the logical AND of the word data in "Rj" and the word data in "Ri", stores the Instruction bit pattern : 1000 0010 0010 0011 AND (And Word Data of Source Register to Destination Register) 110 7.15 AND (And Word Data of Source Register to Data in 112 7.16 ANDH (And Half-word Data of Source Register to Data in 114 7.17 ANDB (And Byte Data of Source Register to Data in 115 91Example: ANDB R2, @R3Instruction bit pattern : 1000 0110 0010 0011 Before execution After execution 116 7.18 OR (Or Word Data of Source Register to Destination Takes the logical OR of the word data in "Ri" and the word data in "Rj", stores the Instruction bit pattern : 1001 0010 0010 0011 OR (Or Word Data of Source Register to Destination Register) 117 7.19 OR (Or Word Data of Source Register to Data in Memory)118 94Example: OR R2, @R3Instruction bit pattern : 1001 0100 0010 0011 Before execution After execution 119 7.20 ORH (Or Half-word Data of Source Register to Data in 120 96Example: ORH R2, @R3Instruction bit pattern : 1001 0101 0010 0011 Before execution After execution 121 7.21 ORB (Or Byte Data of Source Register to Data in Memory)123 7.22 EOR (Exclusive Or Word Data of Source Register to Instruction bit pattern : 1001 1010 0010 0011 124 7.23 EOR (Exclusive Or Word Data of Source Register to Data in 125 101Example: EOR R2, @R3Instruction bit pattern : 1001 1100 0010 0011 Before execution After execution 126 7.24 EORH (Exclusive Or Half-word Data of Source Register to 127 103Example: EORH R2, @R3Instruction bit pattern : 1001 1101 0010 0011 Before execution After execution 128 7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory)129 105Example: EORB R2, @R3Instruction bit pattern : 1001 1110 0010 0011 Before execution After execution 130 7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte 132 7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte 134 7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte 136 7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte 138 7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte 139 115Example: BEORL #1, @R3Before execution After execution Instruction bit pattern : 140 7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte 141 117Example: BEORH #1, @R3Before execution After execution Instruction bit pattern : 142 7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory)Instruction bit pattern : 143 7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory)Instruction bit pattern : 144 7.34 MUL (Multiply Word Data)146 7.35 MULU (Multiply Unsigned Word Data)148 7.36 MULH (Multiply Half-word Data)150 7.37 MULUH (Multiply Unsigned Half-word Data)152 7.38 DIV0S (Initial Setting Up for Signed Division)154 7.39 DIV0U (Initial Setting Up for Unsigned Division)156 7.40 DIV1 (Main Process of Division)158 7.41 DIV2 (Correction when Remainder is 0)This instruction is used in signed division. It should be used in combinations such as DIV2 (Correction when Remainder is 0) 160 7.42 DIV3 (Correction when Remainder is 0)This instruction is used in signed division. It should be used in combinations such as Instruction bit pattern : 1001 1111 0110 0000 DIV3 (Correction when Remainder is 0) 161 7.43 DIV4S (Correction Answer for Signed Division)This instruction is used in signed division. It should be used in combinations such as Instruction bit pattern : 1001 1111 0111 0000 DIV4S (Correction Answer for Signed Division) 162 7.44 LSL (Logical Shift to the Left Direction)Instruction bit pattern : 1011 0110 0010 0011 LSL (Logical Shift to the Left Direction) 163 7.45 LSL (Logical Shift to the Left Direction)Instruction bit pattern : 164 7.46 LSL2 (Logical Shift to the Left Direction)Makes a logical left shift of the word data in "Ri" by "{u4 + 16}" bits, stores the results to LSL2 (Logical Shift to the Left Direction)Instruction bit pattern : 165 7.47 LSR (Logical Shift to the Right Direction)Instruction bit pattern : 1011 0010 0010 0011 LSR (Logical Shift to the Right Direction) 166 7.48 LSR (Logical Shift to the Right Direction)Instruction bit pattern : 167 7.49 LSR2 (Logical Shift to the Right Direction)Instruction bit pattern : 168 7.50 ASR (Arithmetic Shift to the Right Direction)Makes an arithmetic right shift of the word data in "Ri" by "Rj" bits, stores the result to Instruction bit pattern : 1011 1010 0010 0011 Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the ASR (Arithmetic Shift to the Right Direction) 169 7.51 ASR (Arithmetic Shift to the Right Direction)Makes an arithmetic right shift of the word data in "Ri" by "u4" bits, stores the result to ASR (Arithmetic Shift to the Right Direction)Instruction bit pattern : 170 7.52 ASR2 (Arithmetic Shift to the Right Direction)Instruction bit pattern : 171 7.53 LDI:32 (Load Immediate 32-bit Data to Destination Loads 1 word of immediate data to "Ri". LDI:32 (Load Immediate 32-bit Data to Destination Register)Instruction bit pattern : 1001 1111 1000 0011 : 1000 0111 0110 0101 : 0100 0011 0010 0001 172 7.54 LDI:20 (Load Immediate 20-bit Data to Destination Instruction bit pattern : 1001 1011 0101 0011 : 0100 0011 0010 0001 173 7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)Instruction bit pattern : 1100 0010 0001 0011 174 7.56 LD (Load Word Data in Memory to Register)Loads the word data at memory address "Rj" to "Ri".Instruction bit pattern : 0000 0100 0010 0011 175 7.57 LD (Load Word Data in Memory to Register)Loads the word data at memory address "(R13 + Rj)" to "Ri".Instruction bit pattern : 0000 0000 0010 0011 176 7.58 LD (Load Word Data in Memory to Register)Loads the word data at memory address "(R14 + o8 4)" to "Ri".Instruction bit pattern : 177 7.59 LD (Load Word Data in Memory to Register)Instruction bit pattern : 178 7.60 LD (Load Word Data in Memory to Register)Instruction bit pattern : 0000 0111 0000 0011 179 7.61 LD (Load Word Data in Memory to Register)180 156Example: LD @ R15 +, MDHInstruction bit pattern : 0000 0111 1000 0100 Before execution After execution 181 7.62 LD (Load Word Da t a i n M em o ry to Program Status Register)183 7.63 LDUH (Load Half-word Data in Memory to Register)Extends with zeros the half-word data at memory address "Rj", loads to "Ri".Instruction bit pattern : 0000 0101 0010 0011 184 7.64 LDUH (Load Half-word Data in Memory to Register)Extends with zeros the half-word data at memory address "(R13 + Rj)", loads to "Ri".Instruction bit pattern : 0000 0001 0010 0011 185 7.65 LDUH (Load Half-word Data in Memory to Register)Extends with zeros the half-word data at memory address "(R14 + o8 2)", loads to Instruction bit pattern : 186 7.66 LDUB (Load Byte Data in Memory to Register)Extends with zeros the byte data at memory address "Rj", loads to "Ri".Instruction bit pattern : 0000 0110 0010 0011 187 7.67 LDUB (Load Byte Data in Memory to Register)Extends with zeros the byte data at memory address "(R13 + Rj)", loads to "Ri".Instruction bit pattern : 0000 0010 0010 0011 188 7.68 LDUB (Load Byte Data in Memory to Register)Extends with zeros the byte data at memory address "(R14 + o8)", loads to "Ri".Instruction bit pattern : 189 7.69 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address "Rj".Instruction bit pattern : 0001 0100 0010 0011 190 7.70 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address "(R13 + Rj)".Instruction bit pattern : 0001 0000 0010 0011 191 7.71 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address "(R14 + o8 4)".Instruction bit pattern : 192 7.72 ST (Store Word Data in Register to Memory)Instruction bit pattern : 193 7.73 ST (Store Word Data in Register to Memory)Instruction bit pattern : 0001 0111 0000 0011 194 7.74 ST (Store Word Data in Register to Memory)Instruction bit pattern : 0001 0111 1000 0100 195 7.75 ST (Store Word Data in Program Status Register to Memory)Instruction bit pattern : 0001 0111 1001 0000 196 7.76 STH (Store Half-word Data in Register to Memory)Stores the half-word data in "Ri" to memory address "Rj".Instruction bit pattern : 0001 0101 0010 0011 197 7.77 STH (Store Half-word Data in Register to Memory)Stores the half-word data in "Ri" to memory address "(R13 + Rj)".Instruction bit pattern : 0001 0001 0010 0011 198 7.78 STH (Store Half-word Data in Register to Memory)Stores the half-word data in "Ri" to memory address "(R14 + o8 2)".Instruction bit pattern : 199 7.79 STB (Store Byte Data in Register to Memory)Stores the byte data in "Ri" to memory address "Rj".Instruction bit pattern : 0001 0110 0010 0011 200 7.80 STB (Store Byte Data in Register to Memory)Stores the byte data in "Ri" to memory address "(R13 + Rj)".Instruction bit pattern : 0001 0010 0010 0011 201 7.81 STB (Store Byte Data in Register to Memory)Stores the byte data in "Ri" to memory address "(R14 + o8)".Instruction bit pattern : 202 7.82 MOV (Move Word Data in Source Register to Destination Moves the word data in "Rj" to "Ri".Instruction bit pattern : 1000 1011 0010 0011 203 7.83 MOV (Move Word Data in Source Register to Destination Instruction bit pattern : 1011 0111 0101 0011 204 7.84 MOV (Move Word Data in Program Status Register to Instruction bit pattern : 0001 0111 0001 0011 205 7.85 MOV (Move Word Data in Source Register to Destination Instruction bit pattern : 1011 0011 0101 0011 206 7.86 MOV (Move Word Data in Source Register to Program Status Register)208 7.87 JMP (Jump)Branches to the address indicated by "Ri". JMP (Jump)Instruction bit pattern : 1001 0111 0000 0001 209 7.88 CALL (Call Subroutine)Instruction bit pattern : 1101 0000 1001 0000 210 7.89 CALL (Call Subroutine)Instruction bit pattern : 1001 0111 0001 0001 211 7.90 RET (Return from Subroutine)Branches to the address indicated by the return pointer (RP). RET (Return from Subroutine)Instruction bit pattern : 1001 0111 0010 0000 212 7.91 INT (Software Interrupt)214 7.92 INTE (Software Interrupt for Emulator)216 7.93 RETI (Return from Interrupt)218 7.94 Bcc (Branch Relative if Condition Satisfied)220 7.95 JMP:D (Jump)Instruction bit pattern : 1001 1111 0000 0001 Before execution of "JMP" instruction After branching 221 7.96 CALL:D (Call Subroutine)223 7.97 CALL:D (Call Subroutine)225 7.98 RET:D (Return from Subroutine)227 7.99 Bcc:D (Branch Relative if Condition Satisfied)229 7.100 DMOV (Move Word Data from Direct Address to Register)Instruction bit pattern : 230 7.101 DMOV (Move Word Data from Register to Direct Address)Instruction bit pattern : 231 7.102 DMOV (Move Word Data from Direct Address to Post 232 208Example: DMOV @88H, @R13+Before execution After execution Instruction bit pattern : 233 7.103 DMOV (Move Word Data from Post Increment Register 234 210Example: DMOV @R13+, @54HInstruction bit pattern : Before execution After execution 235 7.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address)237 7.105 DMOV (Move Word Data from Post Increment Register 238 214Example: DMOV @R15+, @38HInstruction bit pattern : Before execution After execution 239 7.106 DMOVH (Move Half-word Data from Direct Address to Instruction bit pattern : 240 7.107 DMOVH (Move Half-word Data from Register to Direct Address)Instruction bit pattern : 241 7.108 DMOVH (Move Half-word Data from Direct Address to Post 242 218Example: DMOVH @88H, @R13+ Instruction bit pattern : Before execution After execution 243 7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address)244 220Example: DMOVH @R13+, @52H Before execution After execution Instruction bit pattern : 245 7.110 DMOVB (Move Byte Data from Direct Address to Register)Instruction bit pattern : 246 7.111 DMOVB (Move Byte Data from Register to Direct Address)Instruction bit pattern : 247 7.112 DMOVB (Move Byte Data from Direct Address to Post 249 7.113 DMOVB (Move Byte Data from Post Increment Register 251 7.114 LDRES (Load Word Data in Memory to Resource)252 7.115 STRES (Store Word Data in Resource to Memory)Instruction bit pattern : 1011 1101 1000 0010 253 7.116 COPOP (Coprocessor Operation)255 7.117 COPLD (Load 32-bit Data from Register to Coprocessor 257 7.118 COPST (Store 32-bit Data from Coprocessor Register to 259 7.119 COPSV (Save 32-bit Data from Coprocessor Register to 261 7.120 NOP (No Operation)This instruction performs no operation. NOP (No Operation)Instruction bit pattern : 1001 1111 1010 0000 262 7.121 ANDCCR (And Condition Code Register and Immediate Data)Instruction bit pattern : 1000 0011 1111 1110 263 7.122 ORCCR (Or Condition Code Register and Immediate Data)Instruction bit pattern : 1001 0011 0001 0000 264 7.123 STILM (Set Immediate Data to Interrupt Level Mask 265 7.124 ADDSP (Add Stack Pointer and Immediate Data)Instruction bit pattern : 266 7.125 EXTSB (Sign Extend from Byte Data to Word Data)Instruction bit pattern : 1001 0111 1000 0001 267 7.126 EXTUB (Unsign Extend from Byte Data to Word Data)Instruction bit pattern : 1001 0111 1001 0001 268 7.127 EXTSH (Sign Extend from Byte Data to Word Data)Instruction bit pattern : 1001 0111 1010 0001 269 7.128 EXTUH (Unsigned Extend from Byte Data to Word Data)Instruction bit pattern : 1001 0111 1011 0001 270 7.129 LDM0 (Load Multiple Registers)272 7.130 LDM1 (Load Multiple Registers)274 7.131 STM0 (Store Multiple Registers)276 7.132 STM1 (Store Multiple Registers)278 7.133 ENTER (Enter Function)279 255Example: ENTER #0CH Before execution After execution Instruction bit pattern : 280 7.134 LEAVE (Leave Function)282 7.135 XCHB (Exchange Byte Data)283 259Example: XCHB @R1, R0Instruction bit pattern : 1000 1010 0001 0000 Before execution After execution 287 A.1 Symbols Used in Instruction Lists289 A.2 Instruction Lists275 APPENDIX B Instruction Maps 299 B.1 Instruction MapThis section shows instruction maps for FR family CPU. Instruction MapTable B.1-1 Instruction Map 300 B.2 "E" FormatThis section shows "E" format for FR family CPU. "E" Format 302 Index
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