Fujitsu CM71-00101-5E ,

9

CHAPTER 2 MEMORY ARCHITECTURE

■Contents of Vector Table Areas

A vector table is composed of entry addresses for each of the "EIT" processing programs. Each table

contains some values whose use is fixed according to the CPU architecture, and some that vary according

to the types of built-in peripheral circuits present. Table 2.1-1 shows the structure of a vector table area.

*: Even when the "TBR" value is changed, the reset vector remains the fixed address "000FFFFCH".

■Vector Table Area Initial Value

After a reset, the value of the table base register (TBR) is initialized to "000FFC00H", so that the vector

table area is between addresses "000FFC00H" and "000FFFFFH".

Table 2.1-1 Structure of a Vector Table Area

Offset from

TBR Number

(hex) Model-

dependent EIT value description Remarks

000HFFHNo INT #0FFH

004HFEHNo INT #0FEH

2F8H41HNo System reserved Do not use

2FCH40HNo System reserved

33CH30HNo INT #030H

340H2FHYes INT #02FH or IR31 Values will increase

towards higher limits

when using over 32-

source extension.

Refer to User’s Manual

for each model.

344H2EHYes INT #02EH or IR30

3BCH10HYes INT #010H or IR00

3C0H0FHNo INT #00FH or NMI

3C4H0EHNo Undefined instruction exception

3C8H0DHNo Emulator exception

3CCH0CHNo Step trace break trap

3D0H0BHNo Operand break trap

3D4H0AHNo Instruction break trap

3D8H09HNo Emulator exception

3DCH08HNo INT #008H or coprocessor error trap

3E0H07HNo INT #007H or coprocessor not-found

trap

3E4H06HNo System reserved Do not use

3F8H01HYes System reserved or Mode Vector Refer to User’s Manual for

each model.

3FCH00HNo Reset *

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Contents

Main Page Page Page PREFACE Objectives and intended reader Trademark Organization of this manual iii Copyright 1997-2007 FUJITSU LIMITED All rights reserved. Page CONTENTS CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ............. 53 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ................................................ 67 Page Page Page Page Main changes in this edition Page Page Page Page Page Page Page Page Page Page 1.1 Features of the FR Family CPU Core 3 CHAPTER 1 FR FAMILY OVERVIEW 1.2 Sample Configuration of an FR Family Device Figure 1.2-1 Sample Configuration of an FR Family Device 4 CHAPTER 1 FR FAMILY OVERVIEW decoder 1.3 Sample Configuration of the FR Family CPU Figure 1.3-1 Sample Configuration of the FR Family CPU Page 2.1 FR Family Memory Space Unused Vector Table Area 2.1.1 Direct Address Area Use of Operand Information Contained in Instructions 8 CHAPTER 2 MEMORY ARCHITECTURE 2.1.2 Vector Table Area Contents of Vector Table Areas Vector Table Area Initial Value 10 CHAPTER 2 MEMORY ARCHITECTURE 2.2 Bit Order and Byte Order 2.3 Word Alignment Data Restrictions on Word Alignment Page Page 14 CHAPTER 3 REGISTER DESCRIPTIONS 3.1 FR Family Register Configuration Figure 3.1-1 FR Family Register Configuration 3.2 General-purpose Registers Special Uses of General-purpose Registers Relation between "R15" and Stack Pointer Initial Value of General-purpose Registers 3.3 Dedicated Registers 3.3.1 Program Counter (PC) 3.3.2 Program Status (PS) PS Unused UnusedILM SCR CCR Bit no. System Condition Code Register (SCR: Bit 10 to bit 08) Condition Code Register (CCR: Bit 07 to bit 00) CCR - - SINZVC Initial value: --00XXXX Note on PS Register 3.3.3 Table Base Register (TBR) Page 3.3.4 Return Pointer (RP) Page 3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP) Stack Pointer Configuration Functions of the System Stack Pointer and User Stack Pointer Recovery from EIT handler 3.3.6 Multiplication/Division Register (MD) Page CHAPTER 4 RESET AND "EIT" PROCESSING Page 4.1 Reset Processing 4.2 Basic Operations in "EIT" Processing 35 CHAPTER 4 RESET AND "EIT" PROCESSING Vector Table Configuration 36 CHAPTER 4 RESET AND "EIT" PROCESSING Saved Registers Recovery from EIT handler 4.3 Interrupts 4.3.1 User Interrupts Time to Start of Interrupt Processing "PC" Values Saved for Interrupts How to Use User Interrupts 4.3.2 Non-maskable Interrupts (NMI) Page 4.4 Exception Processing 4.4.1 Undefined Instruction Exceptions 4.5 Traps 4.5.1 "INT" Instructions 4.5.2 "INTE" Instruction 4.5.3 Step Trace Traps 4.5.4 Coprocessor Not Found Traps 4.5.5 Coprocessor Error Trap Saving and Restoring Coprocessor Error Information 4.6 Priority Levels Priority of Multiple Processes Page 5.1 Pipeline Operation 5.2 Pipeline Operation and Interrupt Processing Conditions that Are Actually Generated How to Avoid Mismatched Pipeline Conditions 5.3 Register Hazards Interlocking 5.4 Delayed Branching Processing Overview of Branching with Delayed Branching Instructions Instructions Prohibited in Delay Slots Restrictions on Interrupts during Processing of Delayed Branching Instructions 5.4.1 Processing Non-delayed Branching Instructions 5.4.2 Processing Delayed Branching Instructions Examples of Programing Delayed Branching Instructions Page 6.1 Instruction Formats The FR family CPU uses six types of instruction format, TYPE-A through TYPE-F. Instruction Formats Relation between Bit Patterns "Ri" and "Rj" and Register Values Relation between Bit Pattern "Rs" and Register Values 6.2 Instruction Notation Formats CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Page Page Page Page 7.1 ADD (Add Word Data of Source Register to Destination Instruction bit pattern : 1010 0110 0010 0011 7.2 ADD (Add 4-bit Immediate Data to Destination Register) Instruction bit pattern : 1010 0100 0010 0011 7.3 ADD2 (Add 4-bit Immediate Data to Destination Register) Instruction bit pattern : 1010 0101 1110 0011 7.4 ADDC (Add Word Data of Source Register and Carry Bit to Instruction bit pattern : 1010 0111 0010 0011 7.5 ADDN (Add Word Data of Source Register to Destination Instruction bit pattern : 1010 0010 0010 0011 7.6 ADDN (Add Immediate Data to Destination Register) Instruction bit pattern : 7.7 ADDN2 (Add Immediate Data to Destination Register) Instruction bit pattern :1010 0001 1110 0011 7.8 SUB (Subtract Word Data in Source Register from Instruction bit pattern : 1010 1100 0010 0011 7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) Subtracts the word data in "Rj" and the carry bit from the word data in "Ri", stores Instruction bit pattern : 1010 1101 0010 0011 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) 7.10 SUBN (Subtract Word Data in Source Register from Instruction bit pattern : 1010 1110 0010 0011 7.11 CMP (Compare Word Data in Source Register and Instruction bit pattern : 1010 1010 0010 0011 7.12 CMP (Compare Immediate Data of Source Register and Instruction bit pattern : 7.13 CMP2 (Compare Immediate Data and Destination Register) Instruction bit pattern : 7.14 AND (And Word Data of Source Register to Destination Takes the logical AND of the word data in "Rj" and the word data in "Ri", stores the Instruction bit pattern : 1000 0010 0010 0011 AND (And Word Data of Source Register to Destination Register) 7.15 AND (And Word Data of Source Register to Data in 87 Example: AND R2, @R3 Instruction bit pattern : 1000 0100 0010 0011 7.16 ANDH (And Half-word Data of Source Register to Data in 89 Example: ANDH R2, @R3 Instruction bit pattern : 1000 0101 0010 0011 7.17 ANDB (And Byte Data of Source Register to Data in 91 Example: ANDB R2, @R3 Instruction bit pattern : 1000 0110 0010 0011 Before execution After execution 7.18 OR (Or Word Data of Source Register to Destination Takes the logical OR of the word data in "Ri" and the word data in "Rj", stores the Instruction bit pattern : 1001 0010 0010 0011 OR (Or Word Data of Source Register to Destination Register) 7.19 OR (Or Word Data of Source Register to Data in Memory) 94 Example: OR R2, @R3 Instruction bit pattern : 1001 0100 0010 0011 Before execution After execution 7.20 ORH (Or Half-word Data of Source Register to Data in 96 Example: ORH R2, @R3 Instruction bit pattern : 1001 0101 0010 0011 Before execution After execution 7.21 ORB (Or Byte Data of Source Register to Data in Memory) 98 Example: ORB R2, @R3 Instruction bit pattern : 1001 0110 0010 0011 7.22 EOR (Exclusive Or Word Data of Source Register to Instruction bit pattern : 1001 1010 0010 0011 7.23 EOR (Exclusive Or Word Data of Source Register to Data in 101 Example: EOR R2, @R3 Instruction bit pattern : 1001 1100 0010 0011 Before execution After execution 7.24 EORH (Exclusive Or Half-word Data of Source Register to 103 Example: EORH R2, @R3 Instruction bit pattern : 1001 1101 0010 0011 Before execution After execution 7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory) 105 Example: EORB R2, @R3 Instruction bit pattern : 1001 1110 0010 0011 Before execution After execution 7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte 107 Example: BANDL #0, @R3 Instruction bit pattern : 7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte 109 Example: BANDH #0, @R3 Instruction bit pattern : 7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte 111 Example: BORL #1, @R3 Instruction bit pattern : 7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte 113 Example: BORH #1, @R3 Instruction bit pattern : 7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte 115 Example: BEORL #1, @R3 Before execution After execution Instruction bit pattern : 7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte 117 Example: BEORH #1, @R3 Before execution After execution Instruction bit pattern : 7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory) Instruction bit pattern : 7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory) Instruction bit pattern : 7.34 MUL (Multiply Word Data) 121 Example: MUL R2, R3 Instruction bit pattern : 1010 1111 0010 0011 7.35 MULU (Multiply Unsigned Word Data) 123 Example: MULU R2, R3 Instruction bit pattern : 1010 1011 0010 0011 7.36 MULH (Multiply Half-word Data) 125 Example: MULH R2, R3 Instruction bit pattern : 1011 1111 0010 0011 7.37 MULUH (Multiply Unsigned Half-word Data) 127 Example: MULUH R2, R3 Instruction bit pattern : 1011 1011 0010 0011 7.38 DIV0S (Initial Setting Up for Signed Division) Instruction bit pattern : 1001 0111 0100 0010 7.39 DIV0U (Initial Setting Up for Unsigned Division) Instruction bit pattern : 1001 0111 0101 0010 7.40 DIV1 (Main Process of Division) 133 Example: DIV1 R2 Instruction bit pattern : 1001 0111 0110 0010 7.41 DIV2 (Correction when Remainder is 0) This instruction is used in signed division. It should be used in combinations such as DIV2 (Correction when Remainder is 0) 135 Example: DIV2 R2 Instruction bit pattern : 1001 0111 0111 0010 7.42 DIV3 (Correction when Remainder is 0) This instruction is used in signed division. It should be used in combinations such as Instruction bit pattern : 1001 1111 0110 0000 DIV3 (Correction when Remainder is 0) 7.43 DIV4S (Correction Answer for Signed Division) This instruction is used in signed division. It should be used in combinations such as Instruction bit pattern : 1001 1111 0111 0000 DIV4S (Correction Answer for Signed Division) 7.44 LSL (Logical Shift to the Left Direction) Instruction bit pattern : 1011 0110 0010 0011 LSL (Logical Shift to the Left Direction) 7.45 LSL (Logical Shift to the Left Direction) Instruction bit pattern : 7.46 LSL2 (Logical Shift to the Left Direction) Makes a logical left shift of the word data in "Ri" by "{u4 + 16}" bits, stores the results to LSL2 (Logical Shift to the Left Direction) Instruction bit pattern : 7.47 LSR (Logical Shift to the Right Direction) Instruction bit pattern : 1011 0010 0010 0011 LSR (Logical Shift to the Right Direction) 7.48 LSR (Logical Shift to the Right Direction) Instruction bit pattern : 7.49 LSR2 (Logical Shift to the Right Direction) Instruction bit pattern : 7.50 ASR (Arithmetic Shift to the Right Direction) Makes an arithmetic right shift of the word data in "Ri" by "Rj" bits, stores the result to Instruction bit pattern : 1011 1010 0010 0011 Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the ASR (Arithmetic Shift to the Right Direction) 7.51 ASR (Arithmetic Shift to the Right Direction) Makes an arithmetic right shift of the word data in "Ri" by "u4" bits, stores the result to ASR (Arithmetic Shift to the Right Direction) Instruction bit pattern : 7.52 ASR2 (Arithmetic Shift to the Right Direction) Instruction bit pattern : 7.53 LDI:32 (Load Immediate 32-bit Data to Destination Loads 1 word of immediate data to "Ri". LDI:32 (Load Immediate 32-bit Data to Destination Register) Instruction bit pattern : 1001 1111 1000 0011 : 1000 0111 0110 0101 : 0100 0011 0010 0001 7.54 LDI:20 (Load Immediate 20-bit Data to Destination Instruction bit pattern : 1001 1011 0101 0011 : 0100 0011 0010 0001 7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register) Instruction bit pattern : 1100 0010 0001 0011 7.56 LD (Load Word Data in Memory to Register) Loads the word data at memory address "Rj" to "Ri". Instruction bit pattern : 0000 0100 0010 0011 7.57 LD (Load Word Data in Memory to Register) Loads the word data at memory address "(R13 + Rj)" to "Ri". Instruction bit pattern : 0000 0000 0010 0011 7.58 LD (Load Word Data in Memory to Register) Loads the word data at memory address "(R14 + o8 4)" to "Ri". Instruction bit pattern : 7.59 LD (Load Word Data in Memory to Register) Instruction bit pattern : 7.60 LD (Load Word Data in Memory to Register) Instruction bit pattern : 0000 0111 0000 0011 7.61 LD (Load Word Data in Memory to Register) 156 Example: LD @ R15 +, MDH Instruction bit pattern : 0000 0111 1000 0100 Before execution After execution 7.62 LD (Load Word Da t a i n M em o ry to Program Status Register) 158 Example: LD @ R15 +, PS Instruction bit pattern : 0000 0111 1001 0000 7.63 LDUH (Load Half-word Data in Memory to Register) Extends with zeros the half-word data at memory address "Rj", loads to "Ri". Instruction bit pattern : 0000 0101 0010 0011 7.64 LDUH (Load Half-word Data in Memory to Register) Extends with zeros the half-word data at memory address "(R13 + Rj)", loads to "Ri". Instruction bit pattern : 0000 0001 0010 0011 7.65 LDUH (Load Half-word Data in Memory to Register) Extends with zeros the half-word data at memory address "(R14 + o8 2)", loads to Instruction bit pattern : 7.66 LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address "Rj", loads to "Ri". Instruction bit pattern : 0000 0110 0010 0011 7.67 LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address "(R13 + Rj)", loads to "Ri". Instruction bit pattern : 0000 0010 0010 0011 7.68 LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address "(R14 + o8)", loads to "Ri". Instruction bit pattern : 7.69 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "Rj". Instruction bit pattern : 0001 0100 0010 0011 7.70 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "(R13 + Rj)". Instruction bit pattern : 0001 0000 0010 0011 7.71 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "(R14 + o8 4)". Instruction bit pattern : 7.72 ST (Store Word Data in Register to Memory) Instruction bit pattern : 7.73 ST (Store Word Data in Register to Memory) Instruction bit pattern : 0001 0111 0000 0011 7.74 ST (Store Word Data in Register to Memory) Instruction bit pattern : 0001 0111 1000 0100 7.75 ST (Store Word Data in Program Status Register to Memory) Instruction bit pattern : 0001 0111 1001 0000 7.76 STH (Store Half-word Data in Register to Memory) Stores the half-word data in "Ri" to memory address "Rj". Instruction bit pattern : 0001 0101 0010 0011 7.77 STH (Store Half-word Data in Register to Memory) Stores the half-word data in "Ri" to memory address "(R13 + Rj)". Instruction bit pattern : 0001 0001 0010 0011 7.78 STH (Store Half-word Data in Register to Memory) Stores the half-word data in "Ri" to memory address "(R14 + o8 2)". Instruction bit pattern : 7.79 STB (Store Byte Data in Register to Memory) Stores the byte data in "Ri" to memory address "Rj". Instruction bit pattern : 0001 0110 0010 0011 7.80 STB (Store Byte Data in Register to Memory) Stores the byte data in "Ri" to memory address "(R13 + Rj)". Instruction bit pattern : 0001 0010 0010 0011 7.81 STB (Store Byte Data in Register to Memory) Stores the byte data in "Ri" to memory address "(R14 + o8)". Instruction bit pattern : 7.82 MOV (Move Word Data in Source Register to Destination Moves the word data in "Rj" to "Ri". Instruction bit pattern : 1000 1011 0010 0011 7.83 MOV (Move Word Data in Source Register to Destination Instruction bit pattern : 1011 0111 0101 0011 7.84 MOV (Move Word Data in Program Status Register to Instruction bit pattern : 0001 0111 0001 0011 7.85 MOV (Move Word Data in Source Register to Destination Instruction bit pattern : 1011 0011 0101 0011 7.86 MOV (Move Word Data in Source Register to Program Status Register) Page 7.87 JMP (Jump) Branches to the address indicated by "Ri". JMP (Jump) Instruction bit pattern : 1001 0111 0000 0001 7.88 CALL (Call Subroutine) Instruction bit pattern : 1101 0000 1001 0000 7.89 CALL (Call Subroutine) Instruction bit pattern : 1001 0111 0001 0001 7.90 RET (Return from Subroutine) Branches to the address indicated by the return pointer (RP). RET (Return from Subroutine) Instruction bit pattern : 1001 0111 0010 0000 7.91 INT (Software Interrupt) 189 Example: INT #20H Instruction bit pattern : 0001 1111 0010 0000 7.92 INTE (Software Interrupt for Emulator) 191 Example: INTE Instruction bit pattern : 1001 1111 0011 0000 7.93 RETI (Return from Interrupt) 193 Example: RETI Instruction bit pattern : 1001 0111 0011 0000 7.94 Bcc (Branch Relative if Condition Satisfied) Instruction bit pattern : 1110 1111 0010 1000 7.95 JMP:D (Jump) Instruction bit pattern : 1001 1111 0000 0001 Before execution of "JMP" instruction After branching 7.96 CALL:D (Call Subroutine) Page 7.97 CALL:D (Call Subroutine) Before execution of "CALL" instruction After branching Instruction bit pattern : 1001 1111 0001 0001 7.98 RET:D (Return from Subroutine) Before execution of "RET" instruction After branching Instruction bit pattern : 1001 1111 0010 0000 7.99 Bcc:D (Branch Relative if Condition Satisfied) Instruction bit pattern : 1111 1111 0010 1000 7.100 DMOV (Move Word Data from Direct Address to Register) Instruction bit pattern : 7.101 DMOV (Move Word Data from Register to Direct Address) Instruction bit pattern : 7.102 DMOV (Move Word Data from Direct Address to Post 208 Example: DMOV @88H, @R13+ Before execution After execution Instruction bit pattern : 7.103 DMOV (Move Word Data from Post Increment Register 210 Example: DMOV @R13+, @54H Instruction bit pattern : Before execution After execution 7.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address) 212 Example: DMOV @2CH, @ R15 Instruction bit pattern : Before execution After execution 7.105 DMOV (Move Word Data from Post Increment Register 214 Example: DMOV @R15+, @38H Instruction bit pattern : Before execution After execution 7.106 DMOVH (Move Half-word Data from Direct Address to Instruction bit pattern : 7.107 DMOVH (Move Half-word Data from Register to Direct Address) Instruction bit pattern : 7.108 DMOVH (Move Half-word Data from Direct Address to Post 218 Example: DMOVH @88H, @R13+ Instruction bit pattern : Before execution After execution 7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address) 220 Example: DMOVH @R13+, @52H Before execution After execution Instruction bit pattern : 7.110 DMOVB (Move Byte Data from Direct Address to Register) Instruction bit pattern : 7.111 DMOVB (Move Byte Data from Register to Direct Address) Instruction bit pattern : 7.112 DMOVB (Move Byte Data from Direct Address to Post 224 Example: DMOVB @71H, @R13+ Instruction bit pattern : 7.113 DMOVB (Move Byte Data from Post Increment Register 226 Example: DMOVB @R13+, @57H Instruction bit pattern : 7.114 LDRES (Load Word Data in Memory to Resource) 7.115 STRES (Store Word Data in Resource to Memory) Instruction bit pattern : 1011 1101 1000 0010 7.116 COPOP (Coprocessor Operation) Page 7.117 COPLD (Load 32-bit Data from Register to Coprocessor Page 7.118 COPST (Store 32-bit Data from Coprocessor Register to Page 7.119 COPSV (Save 32-bit Data from Coprocessor Register to Page 7.120 NOP (No Operation) This instruction performs no operation. NOP (No Operation) Instruction bit pattern : 1001 1111 1010 0000 7.121 ANDCCR (And Condition Code Register and Immediate Data) Instruction bit pattern : 1000 0011 1111 1110 7.122 ORCCR (Or Condition Code Register and Immediate Data) Instruction bit pattern : 1001 0011 0001 0000 7.123 STILM (Set Immediate Data to Interrupt Level Mask 7.124 ADDSP (Add Stack Pointer and Immediate Data) Instruction bit pattern : 7.125 EXTSB (Sign Extend from Byte Data to Word Data) Instruction bit pattern : 1001 0111 1000 0001 7.126 EXTUB (Unsign Extend from Byte Data to Word Data) Instruction bit pattern : 1001 0111 1001 0001 7.127 EXTSH (Sign Extend from Byte Data to Word Data) Instruction bit pattern : 1001 0111 1010 0001 7.128 EXTUH (Unsigned Extend from Byte Data to Word Data) Instruction bit pattern : 1001 0111 1011 0001 7.129 LDM0 (Load Multiple Registers) 247 Example: LDM0 (R3, R4) Instruction bit pattern : 7.130 LDM1 (Load Multiple Registers) Instruction bit pattern : 7.131 STM0 (Store Multiple Registers) 251 Example: STM0 (R2, R3) Instruction bit pattern : 7.132 STM1 (Store Multiple Registers) 253 Example: STM1 (R10, R11, R12) Instruction bit pattern : 7.133 ENTER (Enter Function) 255 Example: ENTER #0CH Before execution After execution Instruction bit pattern : 7.134 LEAVE (Leave Function) 257 Example: LEAVE Instruction bit pattern : 1001 1111 1001 0000 7.135 XCHB (Exchange Byte Data) 259 Example: XCHB @R1, R0 Instruction bit pattern : 1000 1010 0001 0000 Before execution After execution Page Page Page A.1 Symbols Used in Instruction Lists Page A.2 Instruction Lists Page Page Page Page Page Page Page Page Page 275 APPENDIX B Instruction Maps B.1 Instruction Map This section shows instruction maps for FR family CPU. Instruction Map Table B.1-1 Instruction Map Higher 4 bits Lower 4 bits B.2 "E" Format This section shows "E" format for FR family CPU. "E" Format Page Index