xiv
136 "7.42 DIV3 (Correction when Remainder is 0)" is changed.
( "Instruction bit pattern : 1001 1111 0110 0000" is added. )
137 "7.43 DIV4S (Correction Answer for Signed Division)" is changed.
( "Instruction bit pattern : 1001 1111 0111 0000" is added. )
138 "7.44 LSL (Logical Shift to the Left Direction)" is changed.
( "Instruction bit pattern : 1011 0110 0010 0011" is added. )
141 "7.47 LSR (Logical Shift to the Right Direction)" is changed.
( "Instruction bit pattern : 1011 0010 0010 0011" is added. )
144 "7.50 ASR (Arithmetic Shift to the Right Direction)" is changed.
( "Instruction bit pattern : 1011 1010 0010 0011" is added. )
147
"7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register)" is changed.
( "Instruction bit pattern : 1001 1111 1000 0011
: 1000 0111 0110 0101
: 0100 0011 0010 0001" is added. )
148
"7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register)" is changed.
( "Instruction bit pattern : 1001 1011 0101 0011
: 0100 0011 0010 0001" is added. )
149 "7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)" is changed.
( "Instruction bit pattern : 1100 0010 0001 0011" is added. )
150 "7.56 LD (Load Word Data in Memory to Register)"is changed.
( "Instruction bit pattern : 0000 0100 0010 0011" is added. )
151 "7.57 LD (Load Word Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0000 0010 0011" is added. )
153 "7.59 LD (Load Word Data in Memory to Register)" is changed.
( "o4" → "u4" )
154 "7.60 LD (Load Word Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0111 0000 0011" is added. )
156 "7.61 LD (Load Word Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0111 1000 0100" is added. )
157 "7.62 LD (Load Word Data in Memory to Program Status Register)" is changed.
Flag change: ( "Ri" → "R15")
158 "7.62 LD (Load Word Data in Memory to Program Status Register)" is changed.
( "Instruction bit pattern : 0000 0111 1001 0000" is added. )
159 "7.63 LDUH (Load Half-word Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0101 0010 0011" is added. )
160 "7.64 LDUH (Load Half-word Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0001 0010 0011" is added. )
162 "7.66 LDUB (Load Byte Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0110 0010 0011" is added. )
Page Changes (For details, refer to main body.)