AMD specifications AMD Turion 64 X2 Mobile Technology Dual-Core Processor, Product Data Sheet

AMD Turion™ 64 X2 Mobile

Technology Dual-Core Processor

Product Data Sheet

•Compatible with Existing 32-Bit Code Base

	– Including support for SSE, SSE2, SSE3*, MMX™,				Socket S1g1 Processor Specific
	3DNow!™ technology, and legacy x86 instructions
	*SSE3 supported by Rev. E and later processors				Features
	– Runs existing operating systems and drivers				• Refer to the Socket S1g1 Processor Functional
	– Local APIC on the chip
						Data Sheet, order# 31731, for functional and
•	AMD64 Technology
						mechanical details of socket S1g1 processors.
	– AMD64 technology instruction set extensions					Refer to the AMD NPT Family 0Fh Processor
	– 64-bit integer registers, 48-bit virtual addresses,					Electrical Data Sheet, order# 31119, for
	40-bit physical addresses					electrical details of socket S1g1 processors.
	– Eight additional 64-bit integer registers (16 total)				•	Packaging
	– Eight additional 128-bit SSE registers (16 total)
						– 638-pin lidless micro PGA package
•	Dual-Core Architecture					– 1.27-mm pin pitch
	– Discrete L1 and L2 cache structures for each core					– 26 x 26 pin grid array
•	Enhanced Virus Protection					– 35 mm x 35 mm organic substrate
						– Compliant with RoHS (EU Directive 2002/95/EC)
	– No Execute (NX) bit in page-translation tables
						with lead used only in small amounts in specifically
	specifies whether code can be executed from the
						exempted applications
	page
					•	Integrated Memory Controller
• HyperTransport™ Technology to I/O Devices
						– Low-latency, high-bandwidth
	– One 16-bit link supporting speeds up to 800 MHz
						– 128-bit DDR2 SDRAM controller operating at up
	(1600 MT/s) or 3.2 Gbytes/s in each direction
						to 333 MHz
• 64-Kbyte 2-Way Associative ECC-Protected
						– Supports up to two unbuffered SO-DIMMs
	L1 Data Cache				•	Electrical Interfaces
	– Two 64-bit operations per cycle, 3-cycle latency
						– HyperTransport™ technology: LVDS-like
• 64-Kbyte 2-Way Associative Parity-Protected
						differential, unidirectional
	L1 Instruction Cache					– DDR2 SDRAM: SSTL_1.8 per JEDEC
	– With advanced branch prediction					specification
•	16-Way Associative ECC-Protected					– Clock, reset, and test signals also use DDR2
	L2 Cache					SDRAM-like electrical specifications.
	– Exclusive cache architecture—storage in addition				•	Power Management
	to L1 caches					– Multiple low-power states including Deeper Sleep
	– Up to 1 Mbyte per L2 cache					(C1E with AltVID)
	– 1 Mbyte and 512-Kbyte options					– System Management Mode (SMM)
•	Machine Check Architecture					– ACPI compliant, including support for processor
	– Includes hardware scrubbing of major					performance states
						– AMD PowerNow!™ technology is designed to
	ECC-protected arrays
						dynamically switch between multiple low-power
						states based on application performance
						requirements.
	Publication #	41407	Revision:	3.02
	Issue Date:	September 2006

Advanced Micro Devices