Electrical Interfaces, Integrated Memory Controller

PID:46878 Rev:3.04 - February 2009

Family 10h AMD Phenom™ II Processor Product Data Sheet

•System Management Mode (SMM)

•ACPI-compliant, including support for processor performance states

•Supported power states: C0, C1, C1E, S0, S1, S3, S4, S5

•Electrical Interfaces

•DDR2 SDRAM: SSTL_1.8 per JEDEC specification

•DDR3 SDRAM: Compliant to JEDEC DDR3 1.5-V SDRAM specification

•Refer to the AMD Family 10h Processor Electrical Data Sheet, order# 40014, for electrical details of AMD Family 10h processors.

•HyperTransport™ Technology to I/O Devices

•HyperTransport 1 and HyperTransport 3 technology supported

•One (1) link, 16-bits in each direction, supporting up to 2000 MT/s or 4.0 GB/s in each direction in HyperTransport Generation 1.0 mode and 4400 MT/s or 8.8 GB/s in each direction in HyperTransport Generation 3.0 mode.

•Integrated Memory Controller

•AMD Memory Optimizer Technology

•Low-latency, high-bandwidth

•Adaptive Prefetching Support

•ECC checking with double-bit detect and single-bit correct

•Supports up to four unbuffered DIMMs

•Package AM2r2

•144-bit DDR2 SDRAM controller operating at frequencies up to 533 MHz

•Package AM3

•144-bit DDR3 SDRAM controller operating at frequencies up to 667 MHz

•Available Packages

•Compliant with RoHS (EU Directive 2002/95/EC) with lead used only in small amounts in specifically exempted applications

•Package AM2r2

•Refer to the AM2r2 Processor Functional Data Sheet, order# 41697, for functional and mechanical details of the AM2r2 package processor.

•940-pin lidded micro PGA

•1.27-mm pin pitch

•31 x 31 row pin array

•Organic C4 die attach

•Package AM3

•Refer to the AM3 Processor Functional Data Sheet, order# 40778, for functional and mechanical details of the AM3 socket.

•938-pin lidded micro PGA