Preliminary Information
AMD Athlon™ Processor Model 4 Revision Guide | 23614K |
20A Speculative SMC Store Followed by an Actual SMC Store May Cause
Products Affected. A4, A5, A6, A7, A9
Normal Specified Operation.
1.A speculative store instruction initiates a request (R) to modify a
2.The speculative store instruction is ultimately not executed because of a branch misprediction. However, the store R is still in flight attempting to bring the line into the data cache in the modified state.
3.The instruction cache, which fetches instructions 16 bytes at a time, is redirected by the branch into the cache line with address A and fetches a portion of the line into the instruction buffer.
4.R then invalidates the instruction cache line with address A and brings the line into the L1 data cache, marking it as modified. However, the instruction buffer, which also contains some bytes from address A, is not invalidated.
5.The instruction fetch mechanism attempts to read the next
6.This instruction cache request for address A hits on the modified line now in the L1 cache, and evicts it from the data cache to the L2.
7.A second store instruction (S) from the instruction buffer is issued into the execution units. S is a
8.The execution of S detects that an instruction request to fetch address A is in flight. However, the store request is given priority. Since it now hits in the L2 and the L2 state is modified, it assumes that the line cannot be in the instruction cache or the instruction buffer.
Potential Effect on System. The processor will execute stale code instructions.
Suggested Workaround. None. This failure has only been observed in internally generated synthetic code.
Resolution Status. No fix planned.
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