Apple 17-INCH manual Intrepid Controller and Buses, Level 2 Cache, Level 3 Cache

CHAPTER 2

Architecture

Level 2 Cache

The data storage for the L2 cache consists of 256 KB of fast static RAM that is built into the microprocessor chip along with the cache controller and tag storage. The built-in L2 cache runs at the same clock speed as the microprocessor.

Level 3 Cache

The data storage for the L3 cache is 1 MB of DDR SRAM running at a clock speed ratio of 5:1. The tag storage for the L3 cache is built into the microprocessor.

Intrepid Controller and Buses

The Intrepid IC provides cost and performance benefits by combining several functions into a single IC. It contains the memory controller, the PCI bus bridge, the Ethernet and FireWire interfaces, and the AGP interface.

Each of the separate communication channels in the Intrepid IC can operate at its full capacity without degrading the performance of the other channels.

In addition to the buses listed in Table 2-1(page 19), the Intrepid IC also has separate interfaces to the physical layer (PHY) ICs for Ethernet and FireWire, and an IIC (inter-IC control bus) interface that is used for configuring the memory subsystem.

Table 2-1	Buses supported by the Intrepid IC
Bus	Destinations	Width of data path	Bus clock speed
MaxBus	Microprocessor	64 bits	167 MHz
Memory	System RAM	64 bits	333 MHz
PCI	AirPort Extreme, CardBus, Boot ROM	32 bits	33 MHz
AGP4X	Graphics IC	32 bits	66 MHz
Ultra ATA-100	Hard drive	16 bits	100 Mbps
ATA-33	SuperDrive	16 bits	33 MHhz

The microprocessor and the I/O controller IC are described in their own sections. The following sections describe the other subsystems that are connected to the Intrepid IC.

Intrepid Controller and Buses 19

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