Asus A7V880 2.4.2 Chipset, SDRAM CAS# Latency [2.5], DRAM Clock [Auto], Sets the DRAM Clock, DRAM Timing [Auto By SPD], NorthBridge VIA KT880 Configuration

2.4.2 Chipset

The Chipset menu items allow you to change the advanced chipset settings. Select an item then press <Enter> to display the sub-menu.

NorthBridge VIA KT880 Configuration

SouthBridge VIA VT8237 Configuration

NorthBridge VIA KT880 Configuration

********	DRAM Timing ********
DRAM Clock		[Auto]
DRAM Timing		[Auto by SPD]
DRAM BUS	Selection	[Auto]
Primary Graphics Adapter		[AGP]
V-Link 8X Supported		[Enabled]
V-Link Data 2X Support		[Disabled]
AGP Mode		[AGP 8X]
AGP Read	Synchronization	[Disabled]
AGP Fast	Write	[Disabled]
Graphics	Aperture Size	[128MB]
AGP Master 1 W/S Read		[Disabled]
AGP Master 1 W/S Write		[Disabled]

DRAM Clock [Auto]

Sets the DRAM Clock.

Configuration options: [Auto] [266 MHz] [333 MHz] [400 MHz]

DRAM Timing [Auto By SPD]

Sets the DRAM timing parameters according to the DRAM SPD (Serial Presence Detect). When set to Manual, you can manually set the DRAM timing parameters through the DRAM sub-items.

Configuration options: [Manual] [Auto By SPD]

The following sub-items appear when the item DRAM Timing item is set to Manual.

SDRAM CAS# Latency [2.5]

Controls the latency between the SDRAM read command and the time the data actually becomes available. Configuration options: [1.5] [2.0] [2.5] [3.0]

ASUS A7V880 motherboard 2-15