Hyper Threading Technology [Enabled]

Allows you to enable or disable the processor Hyper-Threading Technology. Configuration options: [Disabled] [Enabled]

2.4.5Chipset

The Chipset menu allows you to change the advanced chipset settings. Select an item then press <Enter> to display the sub-menu.

Advanced Chipset Settings

 

Configure DRAM Timing by SPD

[Enabled]

Hyper-Path 2

[Auto]

Graphic Adapter Priority

[PCI Express/PCI]

 

 

PEG Buffer Length

[Auto]

Link Latency

[Auto]

PEG Link Mode

[Auto]

PEG Root Control

[Auto]

Slot Power

[Auto]

Configure DRAM Timing by SPD [Enabled]

When this item is enabled, the DRAM timing parameters are set according to the DRAM SPD (Serial Presence Detect). When disabled, you can manually set the DRAM timing parameters through the DRAM sub-items. Configuration options: [Disabled] [Enabled]

The following sub-items appear when the Configure DRAM Timing by SPD item is set to [Disabled].

DRAM CAS# Latency [3 Clocks]

Controls the latency between the SDRAM read command and the time the data actually becomes available. Configuration options: [3 Clocks] [2.5 Clocks] [2 Clocks]

DRAM RAS# Precharge [4 Clocks]

Controls the idle clocks after issuing a precharge command to the DDR SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]

[5 Clocks]

DRAM RAS# to CAS# Delay [4 Clocks]

Controls the latency between the DDR SDRAM active command and the read/write command. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks]

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Chapter 2: BIOS setup