BIOS .IV

Features Chipset

IV. BIOS SOFTWARE

Details of Chipset Features Setup

SDRAM Configuration (By SPD)

This sets the optimal timing for items 2-4. Leave on default setting, depending on the memory modules that you are using. Default setting is By SPD, which configures items 2-4 by reading the contents in the SPD (Serial Presence Detect) device. This 8-pin serial EEPROM device stores critical parameter information about the module, such as memory type, size, speed, voltage interface, and module banks.

SDRAM CAS Latency

This controls the latency between SDRAM read command and the time that the data actually becomes available. Leave on default setting.

SDRAM RAS to CAS Delay

This controls the latency between SDRAM active command and the read/write command. Leave on default setting.

SDRAM RAS Precharge Time

This controls the idle clocks after issuing a precharge command to SDRAM. Leave on default setting.

Enhanced Page Mode Count (Disabled) / Internal Page Detection (Disabled) Leave both on default setting.

SDRAM Pipe Function (Disabled) / SDRAM x111-2111 Mode (Enabled) Leave both on default setting.

I/O Recovery Time (2 BUSCLK)

Timing for ISA cards. Leave on default setting.

Graphics Aperture Size (64MB)

Memory-mapped, graphics data structures can reside in a Graphics Aperture. Leave on default setting.

Frame Buffer Posted Write (Enabled)

Enabling (default) this feature will increase the efficiency of the CPU-to-VGA frame buffer cycle. Leave on default setting.

Force PCI_66 GAT Mode (Enabled)

Enabling this feature will flush the internal PCI/66 buffer before data transfer. Setting this to Disabled may cause some AGP card compatibility problems.

AGP Bus Turbo Mode (Enabled)

Enabling (default) this feature will improve AGP Bus performance. Disable this for AGP compatibility. Leave on default setting.

Passive Release (Enabled)

This is a mechanism that allows concurrency of CPU-to-ISA cycles. When this feature is enabled, it will be possible to re-arbitrate the PCI bus and allow the CPU to access PCI even when the M1543C has been granted the ISA bus.

Delayed Transaction (Disabled)

If Enabled, this frees the PCI Bus during CPU accessing of 8-bit ISA cards that normally consume about 50-60 PCI Clocks without PCI delayed transaction. If PCI Bus Masters cannot use the PCI Bus, leave this on the default setting of Disabled for some ISA cards that are not PCI 2.1 compliant.

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ASUS P5A User’s Manual