Asus P5PL2 4.4.4 Chipset, Advanced Chipset Settings, Configure DRAM Timing by SPD [Enabled]

4.4.4 Chi pset

The Chipset menu allows you to change the advanced chipset settings. Select an item then press <Enter> to display the sub-menu.

Advanced Chipset Settings
Configure DRAM Timing by SPD	[Enabled]
Hyper Path 3	[Auto]
DRAM Throttling Threshold	[Auto]

Booting Graphic Adapter Priority [PCI Express/PCI]

PEG Buffer Length	[Auto]
Link Latency	[Auto]
PEG Root Control	[Auto]
PEG Link Mode	[Auto]
Slot Power	[Auto]
High Priority Port Select	[Disabled]

Enable or disable Configure DRAM Timing by SPD

Select Screen

Select Item

+- Change Option

F1 General Help

F10 Save and Exit

ESC Exit

Advanced Chi pset Setti ngs

Confi gure DRAM Ti mi ng by SPD [Enabl ed]

When this item is enabled, the DRAM timing parameters are set according to the DRAM SPD (Serial Presence Detect). When disabled, you can manually set the DRAM timing parameters through the DRAM sub-items. The following sub-items appear when this item is Disabled.

Configuration options: [Disabled] [Enabled]

DRAM CAS# Latency [5 Clocks]

Controls the latency between the SDRAM read command and the time the data actually becomes available.

Configuration options: [6 Clock] [5 Clocks] [4 Clocks] [3 Clocks]

DRAM RAS# Precharge [4 Clocks]

Controls the idle clocks after issuing a precharge command to the DDR SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]

[5 Clocks] [6 Clocks]

DRAM RAS# to CAS# Delay [4 Clocks]

Controls the latency between the DDR SDRAM active command and the read/write command. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks] [6 Clocks]

DRAM RAS# Activate to Precharge [15 Clocks] Configuration options: [4 Clocks] [5 Clocks] ~ [18 Clocks]

DRAM Write Recovery Time [4 Clocks]

Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks] [6 Clocks]

4-24 Chapter 4: BIOS setup