Atmel AT91SAM9XE-EK

AT91SAM9XE-EK Evaluation Board User Guide 3-3

6311A–ATARM–04-Feb-08

•Two Two-wire Interfaces (TWI)

– Master, Multi-master and Slave Mode Operation

– General Call Supported in Slave Mode

– Connection to PDC Channel to Optimize Data Transfers in Master Mode Only

•IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins

•Required Power Supplies:

– 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL

– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)

– 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter)

– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)

•Available in a 208-pin PQFP Green and a 217-ball LFBGA Green Package

Contents

Main Page Page Section 1 Overview 1.1 Scope 1.2 Deliverables 1.3 AT91SAM9XE-EK Evaluation Board Page Section 2 Setting Up the AT91SAM9XE-EK Board Page Page Page Page Section 3 Board Description 3.1 AT91SAM9XE 512/256/128 Microcontroller Page Page 3-4 AT91SAM9XE-EK Evaluation Board User Guide 6311AATARM04-Feb-08 3.2 Block Diagram 10/100 Ethernet Figure 3-1. AT91SAM9XE512/256/128 Block Diagram ARM926EJ-S Processor EBI 3.3 Microcontroller 3.4 Memory 3.5 Clock Circuitry 3.6 Reset Circuitry 3.7 Shutdown Controller 3.10 Audio Stereo Interface 3.11 User Interface 3.12 Debug Interface 3.13 Expansion Slot 3.14 PIO Usage Table 3-1. PIO Controller A Table 3-2. PIO Controller B Table 3-3. PIO Controller C Section 4 Configuration 4.1 Jumpers Table 4-1. Jumpers Configuration 4.2 JTAG/ICE 4.3 Microcontroller Clock 4.4 Memory Configuration Table 4-2. JTAG/ICE Configuration Table 4-3. Microcontroller Clock Configuration 4.5 Ethernet 4.6 Miscellaneous Refer to the TOP level schematic for the PIO usage. Table 4-5. Miscellaneous Section 5 Schematics 5.1 Schematics Page Page Page Page Page Page Page Page Page Page Headquarters International Product Contact