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Casio G486VPB - page 13

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Locations of Jumpers on the G486VPB

Contents

Main vCopyright 1995 by DFI, Inc. vFCC Statement on Class B v Table of Contents v Page vIntroduction Features and Specifications Page Package Checklist vInstallation Overview Preparing the Area Handling the System Board Tips in Handling the System Board Hardware Installation Installation Procedures Page Cache Configuration To upgrade from 256KB to 512KB of cache memory, use four pieces of 128Kx8 SRAM. Pin 1SRAM Socket Page CPU Installation Page Page Jumpers JP15, JP17 and JP19 CPU External Clock Selection Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Memory Installation PCI/ISA System Board Page Page Page Page Page Page Installing the System Board Page Page Serial Ports Parallel Port Page Floppy Disk Drive Controller IDE Hard Disk Interface Page Page PS/2 Mouse Port Installing Expansion Cards vInitial Setup Program Award BIOS CMOS Setup Utility Standard CMOS Setup Page Page BIOS Features Setup Page Chipset Features Setup Power Management Setup PCI Configuration Setup Load BIOS Defaults Load Setup Defaults Password Setting Page IDE HDD Auto Detection Save & Exit Setup Exit Without Saving vIDE Device Drivers vTroubleshooting Checklist Page vAppendix A: Types of Modules Page vAppendix B: System Error Report POST Beep Error Messages Page Page Page Page vAppendix C: Memory & I/O Maps Memory Address Map I/O Address Map G486VPB vAppendix D: PCI I/O Pin Assignments Component Side Solder Side PCI/ISA System Board vAppendix E: ISA I/O Pin Assignments B G486VPB vAppendix F: Connector Pin Assignments Locations of Connectors on the System Board Page Page Page Page Page Page Page Page Page vAppendix G: Award BIOS Hard Disk Table