JP9: Watchdog Timer Active Type Select

JP9

Description

1

 

 

Short 1-2 (default)

System Reset

 

Short 2-3

Active NMI

 

Open

Disabled

 

 

 

3

JP14: Watchdog Timer Out Period Select

 

Period

PINS 1-2

PINS 3-4

PINS 5-6

PINS 7-8

 

 

 

 

 

 

 

1 sec

Open

Open

Short

Open

 

(default)

 

 

 

 

 

2

2 sec

Open

Open

Short

Short

10 sec

Open

Short

Open

Open

1

20 sec

Open

Short

Open

Short

 

110 sec

Short

Open

Open

Open

 

220 sec

Short

Open

Open

Short

 

The watchdog timer is disabled after the system power-on. The watchdog timer can be enabled by a Enable cycle with reading the control port (443H), a Refresh cycle with reading the control port (443H) and a Disable cycle by reading the watchdog timer disable control port (043H). After a Enable cycle of WDT, user must constantly proceed a Refresh cycle to WDT before its period setting comes ending of every 1, 2, 10, 20, 110 or 220 seconds (Please reference to the selection table of JP14 for WDT Time Out period setting). If the Refresh cycle does not active before WDT period cycle, the onboard WDT architecture will issue a Reset or NMI cycle to the system. The watchdog timer controlled by two I/O ports.

443H

I/O Read

Enable/Refresh cycle

043H

I/O Read

Disable cycle

The following sample program shows how to Enable, Disable and Refresh the watchdog timer

WDT_EN_RF

EQU

0433H

 

WDT_DIS

EQU

0043H

 

WT_Enable

PUSH

AX

; keep AX DX

PUSH

DX

 

 

MOV

DX,WDT_EN_RF

; enable the WDT

IN

AL,DX

 

 

POP

DX

 

; get back AX, DX

POP

AX

 

 

RET

 

 

 

8

7

11