Table 1 shows the results of our compilation and a compari- son of the same function implemented using EZ-USB.
It is the manner in which EZ-USB handles the USB protocols that will need to be addressed when converting from the Intel 8x930Ax to the EZ-USB family. Firmware code which deals with the peripheral function can remain the same, even if the firmware code was previously compiled for the 251 architec- ture. If the firmware code was written in C, then recompiling under the 8051 option instead of the 251 option should keep the effort to convert to Cypress’s EZ-USB to a minimum.
EZ-USB Hardware Considerations Versus the Intel 8x930Ax
While architectural differences on how each of the USB mi- crocontrollers handle the USB protocol must be observed, there are hardware differences which can yield a better USB hardware design. These are:
•Elimination of external ROM or EPROM
•Elimination of external components
•Higher I/O performance -> Yielding maximum USB perfor- mance
•Additional endpoints
•Support of maximum packet sizes for all endpoints
•Lower power/Easier power management
•Smaller board density
•Multiple product options
The firmware developer and hardware designer will need to make slight modifications in order to take advantage of these hardware advantages. The following is a quick summary of these differences and benefits.
1.Elimination of external ROM or EPROM
While the Intel family includes an internal ROM option, most users have implemented the ROMless option (80390Ax) with external ROM or EPROM in order to max- imize flexibility in firmware changes. While the EZ-USB family also supports external firmware memory, the unique EZ-USB ability to download firmware from the host PC eliminates the need for external ROM or EPROM. The EZ-USB firmware download feature provides firmware flex- ibility coupled with the cost advantage of an internal ROM.
2.Elimination of external components
While the Intel family uses a multiplexed address and data- bus, the EZ-USB family has a separate address and data- bus, eliminating the need for an external demultiplexing latch. In addition, with only 16 PIOs of the 8x930Ax com- pared to 24 PIOs of the AN2131QC, USB designs which require additional I/Os may be able to eliminate additional external components.
3.Higher I/O performance -> Yielding maximum USB perfor- mance
Intel’s architecture supports standard transfer whereby the 8051 instructions initiate a data transfer through a MOVX and then increments the address. For high-performance applications, this can result in USB performance limited by the USB microcontroller as the 8051 cannot empty FIFOs fast enough to keep pace with a high data transfer rate. Some users have reported losing data every 3rd frame due to this performance limitation. The suggested solution was to reduce the packet size to 8 or 16 bytes per frame.
However, the EZ-USB has a special data transfer mode called Turbo mode which yields significant USB perfor- mance improvement. With Turbo mode, the EZ-USB core monitors certain “MOVX” transfers, and directly broad- casts or receives their data to or from the databus, and generates read and write strobes. In the bulk Turbo mode, a third datapointer in EZ-USB auto increments the RAM address with each read or write cycle. Thus the bulk data RAM buffer acts as a fast FIFO with the ability to transfer 1 byte in 330 ns. As a result, EZ-USB can support 17 bulk packets of a 64-byte size within a single USB frame (1 ms) in a standard Windows® environment (see white paper on AN2131 bulk performance). In this illustration, perfor- mance was limited by the host controller, not the EZ-USB. The EZ-USB microcontroller never generated a NAK. This yields an equivalent data transfer rate of 8.9 Mbps.
Similarly, in isochronous mode, 8a bytes can be trans- ferred in or out of an ISO endpoint FIFO in 330 ns. Thus a 1024-byte packet can be transferred in or out of an isoch- ronous endpoint FIFO in 1/3 time of a single USB frame providing leftover time for the internal 8051 to perform oth- er functions.
To take advantage of the EZ-USB turbo mode, firmware will need to be adjusted so that read and write operations occur on pins PA4/FWR# and PA5/FRD#.
4.Additional endpoints/Max. endpoints packet size
The Intel 8x930Ax supports 2 endpoint configurations; 4 or 6 endpoint pairs. In either configuration, endpoint 1 is used to support a 64-byte bulk packet size or a 512-byte isochronous packet size. A 1024-byte packet is available, but does not support the USB requirement of an isochro- nous packet being double buffered. Endpoints 2–5 are ei- ther 16- or 32-byte packets.
With EZ-USB, 16 endpoint pairs are available. Endpoints 1 through 7 support 64-byte bulk packet sizes. In addition, to obtain maximum performance, these endpoints can be paired, providing double buffering capability to maximize bulk performance.
For isochronous support, the EZ-USB family provides eight endpoints, numbered 8–15. A full 2 Kbytes of isoch- ronous FIFO is provided, so that a 1024-byte packet (dou- ble buffered) can be supported in a single USB frame.
In converting to the EZ-USB product, bulk peripheral de- signs can still use endpoint 1 for primary data transfers. If the firmware is using other endpoints for control and sta-
