Contents
Main
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141
1K x 8 Dual-Port Static RAM
,
Features
Functional Description
Logic Block Diagram
Pin Configurations
Figure 1. Pin Diagram - DIP (Top View)
Figure 2. Pin Diagram - PLCC (Top View) Figure 3. Pin Diagram - PQFP (Top View)
CY7C130, CY7C130A CY7C131, CY7C131A
Pin Definitions
Selection Guide
CY7C140, CY7C141
Maximum Ratings
Electrical Characteristics
Operating Range
Capacitance
Document #: 38-06002 Rev. *E Page 5 of 19
Parameter Description Test Conditions Max Unit C
Input Capacitance T
= 25C, f = 1 MHz, V
Page
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141
Page
Document #: 38-06002 Rev. *E Page 9 of 19
Figure 5. Read Cycle No. 1
Either Port Address Access
Figure 7. Read Cycle No. 3
Figure 6. Read Cycle No. 2
Document #: 38-06002 Rev. *E Page 10 of 19
Figure 8. Write Cycle No. 1 (OE Three-States Data I/OsEither Port
Figure 9. Write Cycle No. 2 (R/W Three-States Data I/OsEither Port)
(continued)
Either Port
Document #: 38-06002 Rev. *E Page 11 of 19
Figure 10. Busy Timing Diagram No. 1 (CE Arbitration)
Valid First:
Figure 11. Busy Timing Diagram No. 2 (Address Arbitration)
(continued)
Page
CY7C130, CY7C130A CY7C131, CY7C131A
Figure 13. Interrupt Timing Diagrams
Document #: 38-06002 Rev. *E Page 13 of 19
(continued)
Right Side Clears INT
CY7C140, CY7C141
Typical DC and AC Characteristics
Page
Ordering Information
Document #: 38-06002 Rev. *E Page 17 of 19
Package Diagrams
51-80044 **
Figure 14. 48-Pin (600 Mil) Sidebraze DIP D26
Figure 15. 52-Pin Pb-Free Plastic Leaded Chip Carrier J69
MIL-STD-1835 D-14 Config. C
Page
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