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CHAPTER 9 MEMORY ACCESS MODES .................................................................... 161
9.1 Outline of Memory Access Modes ................ .................................................................................. 162
9.1.1 Mode Pins .................................................................................................................................. 163
9.1.2 Mode Data ........................................................................ ......................................................... 164
9.1.3 Memory Space in Eac h Bus Mode ... ......................................................................................... 165
CHAPTER 10 I/O PORTS ................................................................................................ 167
10.1 I/O Ports .......................................................................................................................................... 168
10.2 I/O Port Registers ........................................................................................................................... 169
10.2.1 Port Data Register (PDR) ........... ............................................................................................... 170
10.2.2 Port Direction Register (DDR) ................................................................................................... 172
10.2.3 Pull-up Control Register (PUCR) ................................ ............................................................... 174
10.2.4 Analog Input Enable Register (ADER) .............................................................. ........................ 175
10.2.5 Input Level Select Register ................................................................... ..................................... 176
CHAPTER 11 TIMEBASE TIMER ................................................................................... 179
11.1 Overview of Timebase Timer .......................................................................................................... 180
11.2 Block Diagram of Timebase Timer ..................... ............................................................................ 182
11.3 Configuration of Timebase Timer ....................... ............................................................................ 184
11.3.1 Timebase timer control register (TBTC) .................................................................................... 185
11.4 Interrupt of Timebase Timer ............................... ............................................................................ 187
11.5 Explanation of Operations of Timebase Timer Functions ............................................................... 1 88
11.6 Precautions when Using Timebase Timer .............................................................. ........................ 192
11.7 Program Example of Timebase Timer .......................................................................... .................. 193
CHAPTER 12 WATCHDOG TIMER ................................................................................ 195
12.1 Overview of Watchdog Timer ............................. ............................................................................ 196
12.2 Configuration of Watchdog Timer ................................................................................. .................. 199
12.3 Watchdog Timer Registers .................................................... ......................................................... 201
12.3.1 Watchdog timer control register (WDTC) ....................................................................... ........... 202
12.4 Explanation of Operations of Watchdog Tim er Functions .............................................................. 204
12.5 Precautions when Using Watchdog Timer ...................................................................................... 207
12.6 Program Examples of Watchdog Timer .......................................................................................... 2 08
CHAPTER 13 16-Bit I/O TIMER ...................................................................................... 209
13.1 Overview of 16-bit I/O Timer ........................................................................................................... 210
13.2 Block Diagram of 16-bit I/O Timer ................ .................................................................................. 211
13.2.1 Block Diagram of 16-bit Free-run Timer .................................................................................... 213
13.2.2 Block Diagram of Input Capture ........................................................................ ........................ 214
13.3 Configuration of 16-bit I/O Timer .................. .................................................................................. 216
13.3.1 Timer Control Status Register (Upper) (TCCSH) ...................................................................... 217
13.3.2 Timer Control Status Register (Lower) (TCCSL) ........ ............................................................... 218
13.3.3 Timer Data Register (TCDT) ................................................................................................ ..... 220
13.3.4 Input Capture Control Status Registers (ICS) ......................................................... .................. 221
13.3.5 Input Capture Register (IPCP) .............................................................. ..................................... 223
13.3.6 Input Capture Edge Register (ICE) ....................................................... ..................................... 224
13.4 Interrupts of 16-bit I/O Timer .................. ......................................................................................... 227