Fujitsu F2MCTM-16LX manual - page 9

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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Overview of MB90360 ........................................................................................................................ 2
1.2 Block Diagram of MB90360 series ..................................................................................................... 9
1.3 Package Dimensions .................................... .................................................................................... 12
1.4 Pin Assignment ............................................................................. .................................................... 13
1.5 Pin Functions ................................................ .................................................................................... 14
1.6 Input-Output Circuits ..................................................................... .................................................... 17
1.7 Handling Device ............................................................................................................ ....... ...... ....... 21
CHAPTER 2 CPU ............................................................................................................ 27
2.1 Outline of the CPU ................................................................. ........................................................... 28
2.2 Memory Space ........................................................................................................ .......................... 29
2.3 Memory Map ................................................................................. .................................................... 32
2.4 Linear Addressing ......................................................................... .................................................... 33
2.5 Bank Addressing Types ......................................................... ........................................................... 34
2.6 Multi-byte Data in Memory Space .................................................................... ................................. 36
2.7 Registers ................................................................................................................. ...... ....... ...... ....... 37
2.7.1 Accumulator (A) .................................................................................................................... ....... 40
2.7.2 User Stack Pointer (U SP) and System Stack Pointer (SSP) .......................................... ............. 41
2.7.3 Processor Status (PS) ................................................................................ ................................. 42
2.7.4 Program Counter (PC) ................................................................................................................. 45
2.8 Register Bank .............. ..................................................................................................................... 46
2.9 Prefix Codes ....................... .............................................................................................................. 48
2.10 Interrupt Disable Instructions ............................................................................................................ 51
2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions ...................... .......................... 52
CHAPTER 3 INTERRUPTS ............................................................................................. 55
3.1 Outline of Interrupts ..... ..................................................................................................................... 56
3.2 Interrupt Vector ............................................. .................................................................................... 59
3.3 Interrupt Control Registers (ICR) ........................ .............................................................................. 61
3.4 Interrupt Flow ................................................................................ .................................................... 65
3.5 Hardware Interrupts ...................................... .................................................................................... 67
3.5.1 Hardware Interrupt Ope ration ............................................................................................... ....... 68
3.5.2 Occurrence and Rel ease of Hardware Interrupt ................................................................... ....... 69
3.5.3 Multiple interrupts ....................................................... ................................................................. 71
3.6 Software Interrupts ........................................................................................................................... 72
3.7 Extended Intelligent I/O Service (EI2OS) ......................................................... ................................. 74
3.7.1 Extended Intellig ent I/O Service Descriptor (ISD) ....................................................................... 76
3.7.2 EI2OS Status Register (ISCS) .................................... ................................................................. 78
3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS ) .............. 79
3.9 Exceptions ........................................................................................................................... ..... . ....... 82