647
APPENDIX D List of Interrupt Vectors
Note:
For a peripheral module having two interrupt causes for one interrupt number, an EI2OS interrupt clear
signal clears both interrupt request flags.
When EI2OS ends, an EI2OS clear signal is sent to every interrupt flag assigned to each interrupt
number.
EI2OS is activated when one of two interrupts assigned to an interrupt control register (ICR) is caused
while EI2OS is enabled. This means that an EI2OS descriptor that should essentially be specific to each
interrupt cause is shared by two interrupts. Therefore, while one interrupt is enabled, the other interrupt
must be disabled.
UART 1 RX Y2 #37 FFFF68HICR13 0000BDH
UART 1 TX Y1 #38 FFFF64H
Reserved N #39 FFFF60HICR14 0000BEH
Reserved N #40 FFFF5CH
Flash memory N #41 FFFF58HICR15 0000BFH
Delayed interrupt generation module N #42 FFFF54H
Y1: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag.
Y2: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag. A stop request is issued.
N: An EI2OS interrupt clear signal does not clear the interrupt request flag.
Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2/2)
Interrupt cause EI2OS clear DMA
channel
number
Interrupt vector Interrupt control register
Number ICR Address