Fujitsu MB3773 - page 21

MB3773
21
EXAMPLE 9: Reducing Reset Hold Time
VCC( = 5 V)
1
2
3
4
8
7
6
5
CT
MB3773
RESET
RESET
CK
GND
Logic circuit
(a) TPR reduction method
VCC ( = 5 V)
1
2
3
4
8
7
6
5
CT
MB3773
RESET
RESET
CK
GND
Logic circuit
Notes : • RESET is the only output that can be used.
• Standard TPR, TWD and TWR value can be found using the following formulas.
Formulas:TPR (ms) := 100 × CT (µF)
TWD (ms) := 100 × CT (µF)
TWR (ms) := 16 × CT (µF)
• The above formulas become standard values in determining TPR, TWD and TWR.
Reset hold time is compared below between the reduction circuit and the standard circuit.
(b) Standard usage
CT = 0.1 µF
TPR reduction circuit Standard circuit
TPR := 10 ms 100 ms
TWD := 10 ms 10 ms
TWR := 1.6 ms 2.0 ms