MB3773
24
CRT
1
0.01 µF10 kΩ30 µs
0.1 µF10 kΩ300 µs
EXAMPLE 11: Circuit for Limiting Upper Clock Input Frequency
Notes : • This is an example application to limit upper frequency fH of clock pulses sent from
the microprocessor.
If the CK cycle sent from the microprocessor exceeds fH, the circuit generates a reset signal.
(The lower frequency has already been set using CT.)
• When a clock pulse such as shown below is sent to terminal CK, a short T2 prevents C2 voltage
from reaching the CK input threshold level ( := 1.25 V), and will cause a reset signal to be output.
The T1 value can be found using the following formula :
Example : Setting C and R allow the upper T1 value to be set (See the table below).
VCC (5 V)
1
2
3
4
8
7
6
5
CT
RESET
RESET
CK
GND
R2
R1=10 kΩ
C2
Tr1
T1 := 0.3 C2R2
T2
CK waveform T3
C2 voltage T1
where VCC = 5 V, T3 ≥ 3.0 µs, T2 ≥ 20 µs