IBM PPC440X5 - page 476

DBSR
Debug Status Register
PPC440x5 CPU Core User’s Manual Preliminary
Page 476 of 589 regsumm440core.fm.
September 12, 2002
DBSR
SPR 0x130 Supervisor Read/Clear
See Debug Status Register (DBSR) on page 244.
Figure 10-12. Debug Status Register (DBSR)
0 IDE Imprecise Debug Event
0 Debug event ocurred while MSR[DE] = 1
1 Debug event occurred while MSR[DE] = 0
For synchronous debug events in internal debug
mode, this field indicates whether the correspond-
ing Debug interrupt occurs precisely or impre-
cisely
1 UDE Unconditional Debug Event
0 Event didn’t occur
1 Event occurred
2:3 MRR
Most Recent Reset
00 No reset has occurred since this field was last
cleared by software.
01 Core reset
10 Chip reset
11 System reset
This field is set upon any processor reset to a
value indicating the type of reset.
4 ICMP Instruction Completion Debug Event
0 Event didn’t occur
1 Event occurred
5 BRT Branch Taken Debug Event
0 Event didn’t occur
1 Event occurred
6 IRPT Interrupt Debug Event
0 Event didn’t occur
1 Event occurred
7 TRAP Trap Debug Event
0 Event didn’t occur
1 Event occurred
8 IAC1 IAC 1 Debug Event
0 Event didn’t occur
1 Event occurred
9 IAC2 IAC 2 Debug Event
0 Event didn’t occur
1 Event occurred
10 IAC3 IAC 3 Debug Event
0 Event didn’t occur
1 Event occurred
11 IAC4 IAC 4 Debug Event
0 Event didn’t occur
1 Event occurred
12 DAC1R DAC 1 Read Debug Event
0 Event didn’t occur
1 Event occurred
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 29 30 31
IDE
UDE ICMP IRPT IAC1
MRR BRT IAC2 DAC2W
DAC1R
TRAP
IAC3
IAC4 DAC1W
DAC2R IAC12ATS
IAC34AT
S
RET