IBM PPC440X5 - page 494

INV0–INV3
Instruction Cache Normal Victim 0–3
PPC440x5 CPU Core User’s Manual Preliminary
Page 494 of 589 regsumm440core.fm.
September 12, 2002
INV0–INV3
SPR 0x370–0x373 Supervisor R/W
See Cache Line Replacement Policy on page96.
Figure 10-28. Instruction Cache Normal Victim Registers (INV0–INV3)
0:7 VNDXA Victim Index A (for cache lines with EA[25:26] =
0b00)
For all victim index fields, the number of bits used
to select the cache way for replacement depends
on the implemented cache size. See Table4-3, on
page-98
for more information.
8:15 VNDXB Victim Index B (for cache lines with EA[25:26] =
0b01)
16:23 VNDXC Victim Index C (for cache lines with EA[25:26] =
0b10)
24:31 VNDXD Victim Index D (for cache lines with EA[25:26] =
0b11)
0 78 1516 2324 31
VNDXA VNDXC
VNDXB VNDXD