IBM PPC440X5 - page 496

IVLIM
Instruction Cache Victim Limit
PPC440x5 CPU Core User’s Manual Preliminary
Page 496 of 589 regsumm440core.fm.
September 12, 2002
IVLIM
SPR 0x399 Supervisor R/W
See Cache Locking and Transient Mechanism on page99.
Figure 10-30. Instruction Cache Victim Limit (IVLIM)
0:1 Reserved
2:9 TFLOOR Transient Floor The number of bits in the TFLOOR field varies, depending on the implemented cache size. See
Table4-3, on page -98 for more information.
10:12 Reserved
13:20 TCEILING Transient Ceiling The number of bits in the TCEILING field varies, depending on the implemented cache size. See
Table4-3, on page -98 for more information.
21:23 Reserved
24:31 NFLOOR Normal Floor The number of bits in the NFLOOR field varies, depending on the implemented cache size. See
Table4-3, on page -98 for more information.
012 910 12 13 20 21 23 24 31
TFLOOR NFLOOR
TCEILING