User’s Manual
PPC440x5 CPU Core Preliminary
Page 542 of 589 instalfa.fm.
September 12, 2002
machhw
RT, RA, RB
prod0:31← (RA)16:31 × (RB)0:15
temp0:32← prod0:31 + (RT)
(RT)← temp1:32
349
machhw. CR[CR0]
machhwo XER[SO, OV]
machhwo. CR[CR0]
XER[SO, OV]
machhwu
RT, RA, RB
prod0:31← (RA)16:31 × (RB)0:15
temp0:32← prod0:31 + (RT)
(RT)← temp1:32
352
machhwu. CR[CR0]
machhwuo XER[SO, OV]
machhwuo. CR[CR0]
XER[SO, OV]
machhws
RT, RA, RB
prod0:31← (RA)16:31 × (RB)0:15
temp0:32← prod0:31 + (RT)
if ((prod0= RT0)∧ (RT0≠ temp1)) then
(RT)← (RT0∨31(¬RT0))
else (RT)← temp1:32
350
machhws. CR[CR0]
machhwso XER[SO, OV]
machhwso. CR[CR0]
XER[SO, OV]
machhwsu
RT, RA, RB
prod0:31← (RA)16:31 × (RB)0:15
temp0:32← prod0:31 + (RT)
(RT)← (temp1:32 ∨31temp0)
351
machhwsu. CR[CR0]
machhwsuo XER[SO, OV]
machhwsuo. CR[CR0]
XER[SO, OV]
maclhw
RT, RA, RB
prod0:31← (RA)16:31 × (RB)0:15
temp0:32← prod0:31 + (RT)
(RT)← temp1:32
353
maclhw. CR[CR0]
maclhwo XER[SO, OV]
maclhwo. CR[CR0]
XER[SO, OV]
maclhwu
RT, RA, RB
prod0:31← (RA)16:31 × (RB)0:15
temp0:32← prod0:31 + (RT)
(RT)← temp1:32
356
maclhwu. CR[CR0]
maclhwuo XER[SO, OV]
maclhwuo. CR[CR0]
XER[SO, OV]
maclhws
RT, RA, RB
prod0:31← (RA)16:31 × (RB)0:15
temp0:32← prod0:31 + (RT)
if ((prod0= RT0)∧ (RT0≠ temp1)) then
(RT)← (RT0∨31(¬RT0))
else (RT)← temp1:32
354
maclhws. CR[CR0]
maclhwso XER[SO, OV]
maclhwso. CR[CR0]
XER[SO, OV]
maclhwsu
RT, RA, RB
prod0:31← (RA)16:31 × (RB)0:15
temp0:32← prod0:31 + (RT)
(RT)← (temp1:32 ∨31temp0)
355
maclhwsu. CR[CR0]
maclhwsuo XER[SO, OV]
maclhwsuo. CR[CR0]
XER[SO, OV]
mbar Storage synchronization. All loads and stores that precede the
mbar instruction complete before any loads and stores that fol-
low the instruction access main storage. 357
mcrf BF, BFA Move CR field, (CR[CRn])←(CR[CRm])
where m← BFA and n ← BF 358
mcrxr BF Move XER[0:3] into field CRn, where n←BF.
CR[CRn] ←(XER[SO, OV, CA])
(XER[SO, OV, CA]) ←30359
TableA-1. PPC440x5 Instruction Syntax Summary (continued)
Mnemonic Operands Function Other Registers
Changed Page