User’s Manual
Preliminary PPC440x5 CPU Core
instalfa.fm.
September 12, 2002 Page 551 of 589
sthu RS, D(RA)
Store halfword (RS)16:31 in memory at
EA = (RA|0) + EXTS(D).
Update the base address,
(RA) ←EA.
415
sthux RS, RA, RB
Store halfword (RS)16:31 in memory at
EA = (RA|0) + (RB).
Update the base address,
(RA) ←EA.
416
sthx RS, RA, RB Store halfword (RS)16:31 in memory at
EA = (RA|0) + (RB). 417
stmw RS, D(RA) Store consecutive words from RS through GPR(31) in memory
starting at
EA = (RA|0) + EXTS(D). 418
stswi RS, RA, NB
Store consecutive bytes in memory starting at EA=(RA|0).
Number of bytes n=32 if NB=0, else n=NB.
Bytes are unstacked from CEIL(n/4)
consecutive registers starting with RS.
GPR(0) is consecutive to GPR(31).
418
stswx RS, RA, RB
Store consecutive bytes in memory starting at EA=(RA|0)+(RB).
Number of bytes n=XER[TBC].
Bytes are unstacked from CEIL(n/4)
consecutive registers starting with RS.
GPR(0) is consecutive to GPR(31).
421
stw RS, D(RA) Store word (RS) in memory at
EA = (RA|0) + EXTS(D). 422
stwbrx RS, RA, RB
Store word (RS) byte-reversed in memory at EA= (RA|0) +
(RB).
MS(EA, 4) ←(RS)24:31 || (RS)16:23 ||
(RS)8:15 || (RS)0:7
423
stwcx. RS, RA, RB
Store word (RS) in memory at EA = (RA|0) + (RB)
only if reservation bit is set.
if RESERVE = 1 then
MS(EA, 4) ←(RS)
RESERVE ←0
(CR[CR0]) ←20|| 1|| XERso
else
(CR[CR0]) ←20|| 0|| XERso.
424
stwu RS, D(RA)
Store word (RS) in memory at
EA = (RA|0) + EXTS(D).
Update the base address,
(RA) ←EA.
426
stwux RS, RA, RB
Store word (RS) in memory at
EA = (RA|0) + (RB).
Update the base address,
(RA) ←EA.
427
stwx RS, RA, RB Store word (RS) in memory at
EA = (RA|0) + (RB). 428
TableA-1. PPC440x5 Instruction Syntax Summary (continued)
Mnemonic Operands Function Other Registers
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