User’s Manual
Preliminary PPC440x5 CPU Core
ppc440x5IX.fm.
September 12, 2002 Page 573 of 583
btctrl,277
btl,274
btla,274
btlr,281
btlrl,281
bun,274
buna,274
bunctr,277
bunctrl,277
bunl,274
bunla,274
bunlr,281
bunlrl,281
byte ordering,42
big endian, defined,43
instructions,44,45
little endian, defined,43
structure mapping
big-endian mapping,43
little endian mapping,44
C
cache block, defined,108
cache line
See also cache block
cache line locking,99
cache line replacement policy,96
cache locking transient mechanism,99
cache management instructions
summary
data cache,125
instruction cache,108
caching inhibited,145
CCR0,76,108,110,126,460
CCR1,462
change status management,154
clrlslwi,400
clrlslwi.,400
clrlwi,400
clrlwi.,400
clrrwi,401
clrrwi.,401
cmp,282
cmpi,283
cmpl,284
cmpli,285
cmplw,284
cmplwi,285
cmpw,282
cmpwi,283
cntlzw,286
cntlzw.,286
code
self-modifying,106
coherence
data cache,124
coherency
instruction cache,106
compare
arithmetic,71
logical,71
Condition Register. See also CR
context synchronization,82
control
data cache,125
instruction cache,108
conventions
notational,24
CR,67,464
defined
CR updating instructions,69
instructions
integer
CR,70
crand,287
crandc,288
crclr,294
creqv,289
Critical Input interrupt,178
critical interrupts,161
Critical Save/Restore Register 0,168,169
Critical Save/Restore Register 1,168,169
crmove,292
crnand,290
crnor,291
crnot,291
cror,292
crorc,293
crset,289
crxor,294
CSRR0,168,169,465
CSRR1,168,169,466
CTR,67,467
D
DAC
debug events
applied to instructions that result in multiple storage
accesses,230
applied to various instruction types,230
fields,226
overview,226
processing,229
registers
DAC1–DAC2,246
DAC1–DAC2,246,468
Data Address Compare Register (DAC1),246
data address compareSee also DAC,226