User’s Manual
Preliminary PPC440x5 CPU Core
ppc440x5IX.fm.
September 12, 2002 Page 575 of 583
divwuo,308
divwuo.,308
dlmzb,309
dlmzb.,309
DNV0–DNV3,483
DTV0–DTV3,484
DVC
debug events
applied to instructions that result in multiple storage
accesses,233
applied to various instruction types,233
fields,232
overview,231
processing,233
registers
DVC1–DVC2,246
DVC1–DVC2,246
DVLIM,486
E
E storage attribute,43,146
effective address
calculation,41
endianness,42,146
eqv,310
eqv.,310
ESR,172,487
exception
alignment exception,185
critical input exception,178
data storage exception,181
external input exception,185
illegal instruction exception,187
instruction storage exception,184
instruction TLB miss exception,194
machine check exception,178
privileged instruction exception,187
program exception,187
system call exception,190
trap exception,190
exception priorities,202
exception priorities for
all other instructions,208
allocated load and store instructions,203
branch instructions,207
floating-point load and store instructions,203
integer load, store, and cache management instruc-
tions,202
other allocated instructions,205
other floating-point instructions,204
preserved instructions,207
privileged instructions,205
reserved instructions,207
return from interrupt instructions,207
system call instruction,206
trap instructions,206
Exception Syndrome Register,172
exception syndrome register,172
Exceptions,159
execution synchronization,83
extended mnemonics
bctr,275
bctrl,275
bdnz,270
bdnza,270
bdnzf,270
bdnzfa,270
bdnzfkr,279
bdnzfl,270
bdnzfla,270
bdnzflrl,279
bdnzl,270
bdnzla,270
bdnzlr,279
bdnzlrl,279
bdnzt,270
bdnzta,270
bdnztl,270
bdnztla,270
bdnztlr,279
bdnztlrl,279
bdz,270
bdza,270
bdzf,271
bdzfa,271
bdzfl,271
bdzfla,271
bdzflr,279
bdzflrl,279
bdzl,270
bdzla,270
bdzlr,279
bdzlrl,279
bdzt,271
bdzta,271
bdztl,271
bdztla,271
bdztlr,279
bdztlrl,279
beq,271
beqa,271
beqctr,276
beqctrl,276
beql,271
beqlr,280
beqlrl,280
bf,271
bfa,271
bfctr,276
bfctrl,276