User’s Manual
PPC440x5 CPU Core Preliminary
Page 580 of 583 ppc440x5IX.fm.
September 12, 2002
rlwimi,399
rlwimi.,399
rlwinm,400
rlwinm.,400
rlwnm,403
rlwnm.,403
sc,404
slw,405
slw.,405
sraw,406
sraw.,406
srawi,407
srawi.,407
srw,408
srw.,408
stb,409
stbu,410
stbux,411
stbx,412
sth,413
sthbrx,414
sthu,415
sthux,416
sthx,417
stmw,418
stswi,418
stw,422
stwbrx,423
stwcx.,424
stwu,426
stwux,427
stwx,428
subf,429
subf.,429
subfc,430
subfc.,430
subfco,430
subfco.,430
subfe,431
subfe.,431
subfeo,431
subfeo.,431
subfic,432
subfme,433
subfme.,433
subfmeo,433
subfmeo.,433
subfo,429
subfo.,429
subfze,434
subfze.,434
subfzeo,434
subfzeo.,434
tlbre,435
tlbsx,437
tlbsx.,437
tlbsync,438
tlbwe,439
tw,440
twi,443
wrtee,446
wrteei,447
xor,448
xori,449
instruction address compare See also IAC,222,235
instruction addressing modes,41
instruction cache array organization and operation,95
instruction cache coherency,106
instruction cache controller. See ICC
instruction cache synonyms,107
instruction classes,53
instruction complete (ICMP) debug events,235
instruction fields,520
instruction formats,250,519
diagrams,521
instruction forms,519,521
B-form,522
D-form,522
I-form,522
M-form,524
SC-form,522
X-form,523
XFX-form,524
XL-form,524
XO-form,524
instruction set
classes,53
summary
allocated instructions,63
branch,60
cache management,62
CR logical,61
integer arithmetic,58
integer compare,59
integer logical,59
integer rotate,59
integer shift,60
integer storage access,57
integer trap,59
processor synchronization,61
register management,61
system linkage,61
TLB management,62
instruction set portability,250
instruction set summary,56
instruction storage addressing modes,41
Instruction Storage interrupt,184
instruction storage interrupts,184
Instruction TLB Error Interrupt,194
instruction TLB error interrupts,194
Instructions
classes