User’s Manual
PPC440x5 CPU Core Preliminary
Page 586 of 583 ppc440x5IX.fm.
September 12, 2002
subfze,434
subfze.,434
subfzeo,434
subfzeo.,434
subi,258
subic,259
subic.,260
subis,261
subo,429
subo.,429
supervisor state,80
synchronization
architectural references,82
context,82
execution,83
storage,84
synchronous interrupt class,159
synonyms, instruction cache,107
system call instruction, exception priorities for,206
System Call interrupt,190
T
TBL,513
TBU,514
TCR,213,215,515
time base
defined,209
reading,210
writing,210
timer freeze (debug),238
timers
DEC,211
DECAR,211
decrementer,211
FIT,212
fixed interval timer,212
freezing the timer facilities,217
TCR,215
TSR,216
watchdog timer,213
watchdog timer state machine,215
TLB
entry fields
E,137
EPN,135
ERPN,136
G,137
I,136
M,137
RPN,136
SIZE,135
TID,135
TS,135
U0,136
U1,136
U2,136
U3,136
UR,137
UW,137
UX,137
V,135
W,136
overview,134
shadow arrays,151
TLB management instructions
overview,152
tlbre,435
tlbsx,437
tlbsx.,437
tlbsync,438
tlbwe,439
trace debug mode,221
transient mechanism, cache,99
translation lookaside buffer.See also TLB
trap,441
trap (TRAP) debug events,234
trap instructions
exception priorities for,206
TSR,214,216,516
tw,440
tweq,441
tweqi,444
twge,441
twgei,444
twgle,441
twgt,441
twgti,444
twi,443
twle,441
twlei,444
twlgei,444
twlgt,441
twlgti,444
twlle,441
twllei,444
twllt,441
twllti,444
twlng,441
twlngi,444
twlnl,441
twlnli,444
twlt,441
twlti,444
twne,441
twnei,444
twng,442
twngi,444
twnl,442
twnli,445