User’s Manual
PPC440x5 CPU Core Preliminary
Page 582 of 583 ppc440x5IX.fm.
September 12, 2002
Decrementer,191
External Input,185
Fixed-Interval Timer,192
Floating-Point Unavailable,190
Instruction TLB Error,194
Machine Check,178
Program interrupt,187
System Call,190
Watchdog Timer,192
interrupt (IRPT) debug events,236
interrupt and exception handling registers
ESR,172
interrupt classes
asynchronous,159
critical and non-critical,161
machine check,161
synchronous,159
interrupt controller interface,36
interrupt processing,162
interrupt vector,162
interrupt vector,162
Interrupts,159
interrupts
definitions,175
imprecise,160
order,201
ordering and masking,199
ordering and software,199
partially executed instructions,164
precise,160
registers, processing,165
synchronous and imprecise,160
synchronous and precise,160
types
alignment,185
auxiliary processor unavailable,191
data storage,181
data TLB error,193
debug,195
decrementer,191
definitions,175
external inputs,185
fixed interval timer,192
floating point unavailable,190
instruction storage,184
instruction TLB error,194
machine check,178
program,187
watchdog timer,192
vectors,162
INV0–INV3,494
isel,319
isync,320
ITV0–ITV3,495
IVLIM,496
IVOR0–IVOR15,497
IVPR,498
L
lbz,321
lbzu,322
lbzx,324
lha,325
lhau,326
lhax,328
lhbrx,329
lhz,330
lhzu,331
lhzux,332
lhzx,333
li,258
lis,261
little endian
structure mapping,44
little endian mapping,44
little endian, defined,43
lmw,334
load and store alignment,117
load operations,118
locking, cache lines,99
logical compare,71
LR,66,499
lswi,335
lswx,337
lwarx,339
lwz,341
lwzu,342
lwzux,343
lwzx,344
M
M storage attribute,146
macchw,345
macchws,346
macchwsu,347
macchwu,348
machhw,349
machhwsu,351
machhwu,352
Machine Check,161
Machine Check interrupt,178
machine check interrupts,161,178
Machine State Register. See also MSR
maclhw,353
maclhws,354,390
maclhwu,356
masking and ordering interrupts,199
mbar,357