User’s Manual
Preliminary PPC440x5 CPU Core
ppc440x5IX.fm.
September 12, 2002 Page 583 of 583
mcrf,358
mcrxr,359
MCSR,500
MCSRR0,501
MCSRR1,502
memory coherence required,146
memory management unit,32
memory management. See also MMU
memory map,39
memory organization,39
mfcr,360
mfdcr,361
mfmsr,165,362
mfspr,363
MMU
change status management,154
overview,133
page reference,154
PowerPC Book-E MMU Architecture, nonsupported
features,134
support for Power PC Book-E MMU architecture,133
TLB management instructions
overview,152
read/write (tlbre, tlbwe),153
search (tlbsx),153
MMUCR,148,503
mr,392
mr.,392
MSR,165,504
defined,53
msync,366
mtcr,367
mtcrf,367
mtdcr,368
mtmsr,165
mtspr,370
mulchw,373
mulchwu,374
mulhhw,375
mulhhwu,376
mulhwu,378
mulhwu.,378
mullhw,379
mullhwu,380
mulli,381
mullw,382
mullw.,382
mullwo,382
mullwo.,382
N
nand,383
nand.,383
neg,384
neg.,384
nego,384
nego.,384
nmacchw,385
nmacchws,386
nmachhw,387
nmachhws,388
nmaclhw,389
nmaclhws,390
non-critical interrupts,161
nop,394
nor,391
nor.,391
not,391
not.,391
notation,24,251,520
notational conventions,24
O
opcodes,558,559
allocated instruction,557
preserved instruction,557
operands
storage,39
operations
DCC,116
ICC,104
line flush,121
load,118
store,119
or,392
or.,392
orc,393
orc.,393
ordering
storage access,124
ordering and masking interrupts,199
ori,394
oris,395
P
page management,154
partially executed instructions,164
PID,151,506
PIR,76,507
portability, instruction set,250
precise interrupts,160
prefetch mechanism, speculative,105
preserved instructions, exception priorities for,207
primary opcodes,559
priorities, exception,202
privileged instructions,80